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| motorola.com/semiconductors m68hc08 microcontrollers mc68HC08KH12a data sheet mc68HC08KH12a/d rev. 1 3/2004 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC08KH12a ? rev. 1.0 data sheet motorola data sheet 3 mc68HC08KH12a data sheet to provide the most up-to-date info rmation, the re vision of our documents on the world wide web will be the most current. your printed copy may be an earlier revision. to veri fy you have the latest information available, refer to: http://motorola.com/semiconductors/ the following revision history table summarizes cha nges contained in this document. for your conven ience, the page number designators have been linked to the appropriate location. motorola and the stylized m logo are registered trademarks of motorola, inc. digitaldna is a trademark of motorola, inc. ? motorola, inc., 2004 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . data sheet data sheet mc68HC08KH12a ? rev. 1.0 4 data sheet motorola revision history date revision level description page number(s) mar 2004 0 first general release. ? f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC08KH12a ? rev. 1.0 data sheet motorola list of sections 5 data sheet ? mc68HC08KH12a list of sections section 1. general description . . . . . . . . . . . . . . . . . . . . 19 section 2. memory map . . . . . . . . . . . . . . . . . . . . . . . . . . 29 section 3. random-a ccess memory (ram) . . . . . . . . . . 41 section 4. read-only memory (rom ) . . . . . . . . . . . . . . . 43 section 5. configuration register (config) . . . . . . . . . 45 section 6. central processor unit (cpu) . . . . . . . . . . . . 47 section 7. system integration mo dule (sim) . . . . . . . . . 57 section 8. clock generator module (cgm) . . . . . . . . . . 83 section 9. universal serial bu s module (usb) . . . . . . 109 section 10. monitor rom (mon) . . . . . . . . . . . . . . . . . . 145 section 11. timer interface module (tim) . . . . . . . . . . 157 section 12. input/output (i/o) port s . . . . . . . . . . . . . . . 179 section 13. computer operatin g properly (cop) . . . . 203 section 14. external interrupt (irq ) . . . . . . . . . . . . . . . 209 section 15. keyboard interrupt module (kbi ) . . . . . . . 215 section 16. break module (brk) . . . . . . . . . . . . . . . . . 237 section 17. electrical sp ecifications . . . . . . . . . . . . . . 243 section 18. mechanical specificati ons . . . . . . . . . . . . 251 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . list of sections data sheet mc68HC08KH12a ? rev. 1.0 6 list of sections motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC08KH12a ? rev. 1.0 data sheet motorola table of contents 7 data sheet ? mc68HC08KH12a table of contents section 1. general description 1.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 1.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 1.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 1.4 mcu block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 1.5 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.5.1 64-pin quad flat pack (qf p) . . . . . . . . . . . . . . . . . . . . . . . 23 1.5.2 52-pin low-profile quad flat pack (lqfp) . . . . . . . . . . . . . 24 1.5.3 power supply pins (v dda , v ssa , v dd1 , v ss1 , v dd2 , and v ss2 ) . . . . . . . . . . 25 1.5.4 oscillator pins (osc1 and osc2) . . . . . . . . . . . . . . . . . . . . 26 1.5.5 external reset pin (rst ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.5.6 external interrupt pin (irq1 ) . . . . . . . . . . . . . . . . . . . . . . . .26 1.5.7 usb data pins (dplus0?dplus4 and dminus0?d minus4) . . . . . . . 26 1.5.8 voltage regulator out (regout) . . . . . . . . . . . . . . . . . . . . 26 1.5.9 port a input/output (i/o) pins (pta7?pta0) . . . . . . . . . . . . 27 1.5.10 port b i/o pins (ptb7?p tb0) . . . . . . . . . . . . . . . . . . . . . . . 27 1.5.11 port c i/o pins (ptc4?p tc0) . . . . . . . . . . . . . . . . . . . . . . . 27 1.5.12 port d i/o pins (ptd7/kbd7?ptd0/ kbd0). . . . . . . . . . . . . 27 1.5.13 port e i/o pins (pte4, pte3/kbe3, pte2/kbe2/tch1, pte1/kbe1/tch0, pte0/kbe0/tclk ) . . . . . . . . . . . . . 27 1.5.14 port f i/o pins (p tf7/kbf7?ptf0/kbf0). . . . . . . . . . . . . . 28 section 2. memory map 2.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 2.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents data sheet mc68HC08KH12a ? rev. 1.0 8 table of contents motorola 2.3 i/o section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.4 monitor rom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 section 3. random-access memory (ram) 3.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 3.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 section 4. read-only memory (rom) 4.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 4.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 section 5. configurat ion register (config) 5.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 5.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 5.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 section 6. central pr ocessor unit (cpu) 6.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 6.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.4 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.4.1 accumulator (a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.4.2 index register (h:x). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.4.3 stack pointer (sp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.4.4 program counter (pc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.4.5 condition code register (ccr) . . . . . . . . . . . . . . . . . . . . . . 53 6.5 arithmetic/logic unit (alu) . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents mc68HC08KH12a ? rev. 1.0 data sheet motorola table of contents 9 section 7. system integration module (sim) 7.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 7.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 7.3 sim bus clock control and generation . . . . . . . . . . . . . . . . . . 61 7.3.1 bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 7.3.2 clock start-up from por . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 7.3.3 clocks in stop mode and wait mode . . . . . . . . . . . . . . . . . . 62 7.4 reset and system initializa tion. . . . . . . . . . . . . . . . . . . . . . . . . 62 7.4.1 external pin reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 7.4.2 active resets from inte rnal sources . . . . . . . . . . . . . . . . . . 63 7.4.2.1 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 7.4.2.2 computer operati ng properly (cop) reset. . . . . . . . . . . 65 7.4.2.3 illegal opcode reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 7.4.2.4 illegal address reset . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 7.4.2.5 universal serial bu s reset . . . . . . . . . . . . . . . . . . . . . . . 66 7.5 sim counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 7.5.1 sim counter during power-on rese t . . . . . . . . . . . . . . . . . 67 7.5.2 sim counter during stop mode reco very . . . . . . . . . . . . . . 67 7.5.3 sim counter and reset st ates. . . . . . . . . . . . . . . . . . . . . . . 67 7.6 exception control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 7.6.1 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 7.6.1.1 hardware interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 7.6.1.2 swi instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 7.6.2 interrupt status regist ers. . . . . . . . . . . . . . . . . . . . . . . . . . . 72 7.6.2.1 interrupt stat us register 1 . . . . . . . . . . . . . . . . . . . . . . . . 73 7.6.2.2 interrupt stat us register 2 . . . . . . . . . . . . . . . . . . . . . . . . 74 7.6.2.3 interrupt stat us register 3 . . . . . . . . . . . . . . . . . . . . . . . . 74 7.6.3 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 7.6.4 break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 7.6.5 status flag protection in break mode . . . . . . . . . . . . . . . . . 75 7.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 7.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 7.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 7.8 sim registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents data sheet mc68HC08KH12a ? rev. 1.0 10 table of contents motorola 7.8.1 break status register (bsr) . . . . . . . . . . . . . . . . . . . . . . . .79 7.8.2 reset status register (rsr) . . . . . . . . . . . . . . . . . . . . . . . . 80 7.8.3 break flag control register (bfcr) . . . . . . . . . . . . . . . . . . 81 section 8. clock generator module (cgm) 8.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 8.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 8.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 8.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 8.4.1 crystal oscillator circui t . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 8.4.2 phase-locked loop circ uit (pll) . . . . . . . . . . . . . . . . . . . . 87 8.4.3 pll circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 8.4.4 acquisition and tracking modes . . . . . . . . . . . . . . . . . . . . . 89 8.4.5 manual and automati c pll bandwidth modes. . . . . . . . . . . 89 8.4.6 programming the pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 8.4.7 special program ming exceptions . . . . . . . . . . . . . . . . . . . . 91 8.4.8 base clock selector circ uit . . . . . . . . . . . . . . . . . . . . . . . . . 92 8.4.9 cgm external connectio ns . . . . . . . . . . . . . . . . . . . . . . . . . 92 8.5 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 8.5.1 crystal amplifier input pin (osc1). . . . . . . . . . . . . . . . . . . . 94 8.5.2 crystal amplifier out put pin (osc2) . . . . . . . . . . . . . . . . . . 94 8.5.3 external filter capac itor pin (cgmxfc) . . . . . . . . . . . . . . . 94 8.5.4 pll analog power pin (v dda ) . . . . . . . . . . . . . . . . . . . . . . . 94 8.5.5 pll anal og ground pin (v ssa ) . . . . . . . . . . . . . . . . . . . . . . 94 8.5.6 buffered crystal clock output (c gmvout) . . . . . . . . . . . . 95 8.5.7 cgmvsel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 8.5.8 oscillator enable signal (simoscen). . . . . . . . . . . . . . . . . 95 8.5.9 crystal output frequency signal (cgmxclk) . . . . . . . . . . 95 8.5.10 cgm base clock out put (cgmout). . . . . . . . . . . . . . . . . . 95 8.5.11 cgm cpu interrupt (cgm int) . . . . . . . . . . . . . . . . . . . . . . 95 8.6 cgm registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 8.6.1 pll control register (pctl) . . . . . . . . . . . . . . . . . . . . . . . . 98 8.6.2 pll bandwidth control register (pbwc) . . . . . . . . . . . . . 100 8.6.3 pll multiplier select regist ers (pmsh:pmsl) . . . . . . . . . 101 8.6.4 pll referenc e divider select register (prds) . . . . . . . . 102 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents mc68HC08KH12a ? rev. 1.0 data sheet motorola table of contents 11 8.7 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 8.8 special modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 8.8.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 8.8.2 cgm during break inte rrupts. . . . . . . . . . . . . . . . . . . . . . . 104 8.9 acquisition/lock time spec ifications . . . . . . . . . . . . . . . . . . . 104 8.9.1 acquisition/lock time definitions. . . . . . . . . . . . . . . . . . . .104 8.9.2 parametric influences on reaction time . . . . . . . . . . . . . . 105 8.9.3 choosing a filter capac itor . . . . . . . . . . . . . . . . . . . . . . . . 107 8.9.4 reaction time calculat ion . . . . . . . . . . . . . . . . . . . . . . . . . 107 section 9. universal serial bus module (usb) 9.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 9.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 9.3 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 9.4 i/o register description of the hub function . . . . . . . . . . . . . 112 9.4.1 usb hub root port control r egister (hrpcr) . . . . . . . . 116 9.4.2 usb hub downstream port control register (hdp1cr-hdp4cr) . . . . . . . . . . . . . . . . . . . . . . . . . . .117 9.4.3 usb sie timing interr upt register (sietir) . . . . . . . . . . . 119 9.4.4 usb sie timing stat us register (sietsr) . . . . . . . . . . . . 121 9.4.5 usb hub address r egister (haddr). . . . . . . . . . . . . . . . 123 9.4.6 usb hub interrupt register 0 (hir 0) . . . . . . . . . . . . . . . . 124 9.4.7 usb hub control regi ster 0 (hcr0) . . . . . . . . . . . . . . . . 125 9.4.8 usb hub endpoint1 control & data regi ster (hcdr) . . . 127 9.4.9 usb hub status regist er (hsr). . . . . . . . . . . . . . . . . . . .128 9.4.10 usb hub endpoint 0 data registers 0-7 (he0d0-he0d7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130 9.5 i/o register description of the embedded device function . 130 9.5.1 usb embedded devi ce address register (daddr). . . . . 134 9.5.2 usb embedded device interrupt register 0 (dir0) . . . . . 134 9.5.3 usb embedded device interrupt register 1 (dir1) . . . . . 136 9.5.4 usb embedded device control register 0 (dcr0) . . . . . 137 9.5.5 usb embedded device control register 1 (dcr1) . . . . . 139 9.5.6 usb embedded device status register (dsr ) . . . . . . . . . 140 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents data sheet mc68HC08KH12a ? rev. 1.0 12 table of contents motorola 9.5.7 usb embedded device control register 2 (dcr2) . . . . . 142 9.5.8 usb embedded device e ndpoint 0 data registers (de0d0-de0d7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143 9.5.9 usb embedded device e ndpoint 1/2 data registers (de1d0-de1d7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144 section 10. monitor rom (mon) 10.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145 10.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 10.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 10.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146 10.4.1 entering monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 10.4.2 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 10.4.3 echoing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 10.4.4 break signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 10.4.5 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 10.4.6 baud rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155 section 11. timer interface module (tim) 11.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157 11.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 11.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 11.4 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 11.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159 11.5.1 tim counter prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 11.5.2 input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 11.5.3 output compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 11.5.3.1 unbuffered output compare . . . . . . . . . . . . . . . . . . . . . 162 11.5.3.2 buffered output com pare . . . . . . . . . . . . . . . . . . . . . . .163 11.5.4 pulse width modulatio n (pwm) . . . . . . . . . . . . . . . . . . . . . 163 11.5.4.1 unbuffered pwm sig nal generation . . . . . . . . . . . . . . . 164 11.5.4.2 buffered pwm signal generation . . . . . . . . . . . . . . . . . 165 11.5.4.3 pwm initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents mc68HC08KH12a ? rev. 1.0 data sheet motorola table of contents 13 11.6 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167 11.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 11.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168 11.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168 11.8 tim during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 168 11.9 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 11.9.1 tim clock pin (pte0/tc lk) . . . . . . . . . . . . . . . . . . . . . . .169 11.9.2 tim channel i/o pins (pte1/tch0:pte2/ tch1) . . . . . . . 169 11.10 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 11.10.1 tim status and control register (tsc) . . . . . . . . . . . . . . . 170 11.10.2 tim counter regist ers (tcnth:tcntl) . . . . . . . . . . . . . . 172 11.10.3 tim counter modul o registers (tmodh:tm odl) . . . . . . 173 11.10.4 tim channel status and co ntrol registers (tsc0:tsc1) . 174 11.10.5 tim channel registers (tch0h /l?tch1h/l) . . . . . . . . . . 178 section 12. input/output (i/o) ports 12.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179 12.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 12.3 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 12.3.1 port a data register (pta) . . . . . . . . . . . . . . . . . . . . . . . . 182 12.3.2 data direction register a (ddra) . . . . . . . . . . . . . . . . . . . 182 12.4 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 12.4.1 port b data register (ptb) . . . . . . . . . . . . . . . . . . . . . . . . 184 12.4.2 data direction register b (ddrb) . . . . . . . . . . . . . . . . . . . 185 12.5 port c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 12.5.1 port c data register (ptc) . . . . . . . . . . . . . . . . . . . . . . . . 186 12.5.2 data direction register c (ddrc). . . . . . . . . . . . . . . . . . . 187 12.6 port d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 12.6.1 port d data register (ptd) . . . . . . . . . . . . . . . . . . . . . . . . 189 12.6.2 data direction register d (ddrd). . . . . . . . . . . . . . . . . . . 189 12.7 port e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 12.7.1 port e data register (pte) . . . . . . . . . . . . . . . . . . . . . . . . 191 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents data sheet mc68HC08KH12a ? rev. 1.0 14 table of contents motorola 12.7.2 data direction register e (ddre) . . . . . . . . . . . . . . . . . . . 192 12.7.3 port-e optical interface enable register . . . . . . . . . . . . . . 194 12.8 port f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 12.8.1 port f data register (ptf) . . . . . . . . . . . . . . . . . . . . . . . . 198 12.8.2 data direction register f (ddrf) . . . . . . . . . . . . . . . . . . . 199 12.9 port options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 12.9.1 port option control register (poc) . . . . . . . . . . . . . . . . . . 200 section 13. computer op erating properly (cop) 13.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203 13.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 13.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204 13.4 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 13.4.1 cgmxclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205 13.4.2 copctl write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205 13.4.3 power-on reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 13.4.4 internal reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 13.4.5 reset vector fetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 13.4.6 copd (cop disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 13.4.7 coprs (cop rate sele ct) . . . . . . . . . . . . . . . . . . . . . . . . 206 13.5 cop control register (copctl) . . . . . . . . . . . . . . . . . . . . . . 207 13.6 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207 13.7 monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207 13.8 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 13.8.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208 13.8.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208 13.9 cop module during break mode . . . . . . . . . . . . . . . . . . . . . . 208 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents mc68HC08KH12a ? rev. 1.0 data sheet motorola table of contents 15 section 14. external interrupt (irq) 14.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209 14.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 14.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 14.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .210 14.4.1 irq1 pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 14.5 irq module during break interrupts . . . . . . . . . . . . . . . . . . . 213 14.6 irq status and control register (iscr) . . . . . . . . . . . . . . . . 213 section 15. keyboard in terrupt module (kbi) 15.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215 15.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 15.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 15.4 port-d keyboard interrupt block diagram . . . . . . . . . . . . . . . 218 15.4.1 port-d keyboard inte rrupt functional description . . . . . . . 219 15.4.2 port-d keyboard initiali zation. . . . . . . . . . . . . . . . . . . . . . . 220 15.4.3 port-d keyboard interr upt registers . . . . . . . . . . . . . . . . . 221 15.4.3.1 port-d keyboard status and control register: . . . . . . . 221 15.4.3.2 port-d keyboard interrupt en able register . . . . . . . . . . 222 15.5 port-e keyboard interrupt block diagram . . . . . . . . . . . . . . . 224 15.5.1 port-e keyboard inte rrupt functional description . . . . . . . 225 15.5.2 port-e keyboard initiali zation . . . . . . . . . . . . . . . . . . . . . . . 226 15.5.3 port-e keyboard interr upt registers . . . . . . . . . . . . . . . . . 227 15.5.3.1 port-e keyboard status and control register . . . . . . . . 227 15.5.3.2 port-e keyboard in terrupt enable register . . . . . . . . . . 228 15.6 port-f keyboard interrupt block di agram. . . . . . . . . . . . . . . . 230 15.6.1 port-f keyboard interrupt functi onal description . . . . . . . 231 15.6.2 port-f keyboard initia lization . . . . . . . . . . . . . . . . . . . . . . . 232 15.6.3 port-f keyboard interrupt register s . . . . . . . . . . . . . . . . . 233 15.6.3.1 port-f keyboard status and control register . . . . . . . . 233 15.6.3.2 port-f keyboard interrupt enab le register . . . . . . . . . . 234 15.6.3.3 port-f pull-up enabl e register . . . . . . . . . . . . . . . . . . . 235 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents data sheet mc68HC08KH12a ? rev. 1.0 16 table of contents motorola 15.7 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 15.8 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 15.9 keyboard module during break interrupts . . . . . . . . . . . . . . . 235 section 16. break module (brk) 16.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237 16.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 16.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 16.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238 16.4.1 flag protection during break interr upts . . . . . . . . . . . . . . . 240 16.4.2 cpu during break interrupts . . . . . . . . . . . . . . . . . . . . . . .240 16.4.3 tim during break interr upts . . . . . . . . . . . . . . . . . . . . . . . . 240 16.4.4 cop during break interrupts . . . . . . . . . . . . . . . . . . . . . . . 240 16.5 break module registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 16.5.1 break status and control regist er (brkscr) . . . . . . . . . 241 16.5.2 break address registers (brk h and brkl). . . . . . . . . . . 241 16.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 16.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .242 16.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .242 section 17. electrical specifications 17.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243 17.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 17.3 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 244 17.4 functional operating range. . . . . . . . . . . . . . . . . . . . . . . . . . 245 17.5 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 17.6 dc electrical characterist ics . . . . . . . . . . . . . . . . . . . . . . . . . 246 17.7 control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 17.8 oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents mc68HC08KH12a ? rev. 1.0 data sheet motorola table of contents 17 17.9 timer interface module characterist ics . . . . . . . . . . . . . . . . . 247 17.10 clock generation module characteristics . . . . . . . . . . . . . . . 248 17.10.1 cgm component specifications . . . . . . . . . . . . . . . . . . . . 248 17.10.2 cgm electrical specif ications . . . . . . . . . . . . . . . . . . . . . . 248 17.10.3 acquisition/lock time specifications . . . . . . . . . . . . . . . . . 249 section 18. mechanic al specifications 18.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .251 18.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 18.3 64-pin quad flat pack (qfp) . . . . . . . . . . . . . . . . . . . . . . . . . 252 18.4 52-pin low-profile quad flat pack (lqfp) . . . . . . . . . . . . . . 253 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents data sheet mc68HC08KH12a ? rev. 1.0 18 table of contents motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC08KH12a ? rev. 1.0 data sheet motorola general description 19 data sheet ? mc68HC08KH12a section 1. general description 1.1 contents 1.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 1.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 1.4 mcu block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 1.5 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.5.1 64-pin quad flat pack (qf p) . . . . . . . . . . . . . . . . . . . . . . . 23 1.5.2 52-pin low-profile quad flat pack (lqfp) . . . . . . . . . . . . . 24 1.5.3 power supply pins (v dda , v ssa , v dd1 , v ss1 , v dd2 , and v ss2 ) . . . . . . . . . . 25 1.5.4 oscillator pins (osc1 and osc2) . . . . . . . . . . . . . . . . . . . . 26 1.5.5 external reset pin (rst ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.5.6 external interrupt pin (irq1 ) . . . . . . . . . . . . . . . . . . . . . . . .26 1.5.7 usb data pins (dplus0?dplus4 and dminus0?d minus4) . . . . . . . 26 1.5.8 voltage regulator out (regout) . . . . . . . . . . . . . . . . . . . . 26 1.5.9 port a input/output (i/o) pins (pta7?pta0) . . . . . . . . . . . . 27 1.5.10 port b i/o pins (ptb7?p tb0) . . . . . . . . . . . . . . . . . . . . . . . 27 1.5.11 port c i/o pins (ptc4?p tc0) . . . . . . . . . . . . . . . . . . . . . . . 27 1.5.12 port d i/o pins (ptd7/kbd7?ptd0/ kbd0). . . . . . . . . . . . . 27 1.5.13 port e i/o pins (pte4, pte3/kbe3, pte2/kbe2/tch1, pte1/kbe1/tch0, pte0/kbe0/tclk ) . . . . . . . . . . . . . 27 1.5.14 port f i/o pins (p tf7/kbf7?ptf0/kbf0). . . . . . . . . . . . . . 28 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description data sheet mc68HC08KH12a ? rev. 1.0 20 general description motorola 1.2 introduction the mc68HC08KH12a is a member of the low-cost, high-performance m68hc08 family of 8-bit microcontro ller units (mcus). all mcus in the family use the enhanced m68hc08 c entral processor unit (cpu08) and are available with a variety of mo dules, memory sizes and types, and package types. 1.3 features features of the mc68hc08kh 12a include the following: high-performance m68hc08 architecture fully upward-compatible objec t code with m6805, m146805, and m68hc05 families 6-mhz internal bus operation low-power design (fully stat ic with stop and wait modes) 12k-bytes of user rom with data security 1 384 bytes of on-chip ram 42 general purpose i/o, 29 with software configurable pullups 16 bit, 2-channel timer interface module (tim) 20-bit keyboard interrupt port 5 led direct drive port pins 48-mhz phase-locked loop full universal serial bus spec ification 1.1 composite hub with embedded 2 functions: ?1 12-mhz upstream port ?4 12-mhz/1.5mhz downstream ports 1. no security feature is absolutely secure. howe ver, motorola?s strategy is to make reading or copying the rom difficult for unauthorized users. 2. embedded device supports only bulk and interrupt transfers, and does not support isochronous transfers. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description features mc68HC08KH12a ? rev. 1.0 data sheet motorola general description 21 ?1 hub control endpoint (endpoint 0) with 8 byte transmit buffer and 8 byte receive buffer ?1 hub interrupt endpoint (endpoint 1) with 1 byte transmit buffer ?1 device control endpoint (endpoi nt0) with 8 byte transmit buffer and 8 byte receive buffer ? device interrupt endpoints (e ndpoint1 and endpoint2) share with 8 byte transmit buffer on-chip 3.3v regulator for usb transceiver system protection features ? optional computer operati ng properly (cop) reset ? illegal opcode detecti on with optional reset ? illegal address detecti on with optional reset master reset pin with internal pullup and power-on reset an external asynchronous interrup t pin with internal pullup (irq1 ) 64-pin plastic quad fl at pack (qfp) package , 52-pin low-profile quad flat pack (lqfp) features of the cpu08 include the following: enhanced hc05 programming model extensive loop control functions 16 addressing modes (eight more than the hc05) 16-bit index register and stack pointer memory-to-memory data transfers fast 8 8 multiply instruction fast 16/8 divide instruction binary-coded decimal (bcd) instructions optimization for controller applications third party c lang uage support f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . data sheet mc68hc08k h12a ? rev. 1.0 22 general description motorola general description 1.4 mcu block diagram figure 1-1 shows the structure of the mc68HC08KH12a. figure 1-1. mcu block diagram ds port 1 (1) ports are software configurable with pullup device if input port (2) software configurable led direct drive 3m a source /10ma sink or standard drive (3) pin contains integrated pullup device (4) pin has interrupt capability (5) pin has interrupt and integrated pullup device. (6) pin has optical coupling interface osc1 osc2 rst (3) irq1 (3,4) vdd1 vss1 ptc4?ptc0 (1,2) regout ptb7?ptb0 (1) pta7?pta0 (1) pte3/kbe3? pte0/kbe0 (1,4,6) vdd2 vss2 vssa vdda cgmxfc dplus4 tch0/pte1 tch1/pte2 tclk/pte0 port c ddrc port b ddrb port a ddra port d ddrd port e ddre port f ddrf embedded usb function 384 bytes ram 12k-bytes rom 68hc08 cpu cpu control alu cpu registers accumulator index register stack pointer program counter condition code register v11h i nzc dminus4 dplus3 dminus3 dplus2 dminus2 dplus1 dminus1 dplus0 us port dminus0 monitor rom 240 bytes cop module timer interface module power-on reset module break module irq module system integration module clock generation module and pll power supply and voltage regulation ptd7/kbd7? ptd0/kbd0 (4) ds port 2 ds port 3 ds port 4 ptf7/kbf7? ptf0/kbf0 (1,4) pte4 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description pin assignments mc68HC08KH12a ? rev. 1.0 data sheet motorola general description 23 1.5 pin assignments 1.5.1 64-pin quad flat pack (qfp) figure 1-2 shows the 64-pin qfp assignments. figure 1-2. 64-pin qfp pi n assignment (top view) dminus0 dplus0 regout vssa osc2 osc1 cgmxfc vdda dplus1 dminus1 dplus2 dminus2 dplus3 1 2 3 4 5 6 7 8 9 10 11 12 13 dminus3 dplus4 dminus4 14 15 16 ptb4 ptb5 ptb6 ptb7 pta0 pta1 pta2 pta3 ptb3 ptb2 ptb1 ptb0 ptd7/kbd7 47 46 45 44 42 42 41 40 39 38 37 36 ptd6/kbd6 ptd5/kbd5 ptd4/kbd4 35 34 33 ptf5/kbf5 ptf4/kbf4 ptf3/kbf3 ptf2/kbf2 ptf1/kbf1 ptf0/kbf0 rst irq1 ptf6/kbf6 ptf7/kbf7 vss2 vdd2 pta7 63 62 61 60 59 58 57 56 55 54 53 52 pta6 pta5 pta4 51 50 49 ptc0 vdd1 vss1 pte0/kbe0/tclk pte1/kbe1/tch0 pte2/kbe2/tch1 pte3/kbe3 pte4 ptc1 ptc2 ptc3 ptc4 ptd0/kbd0 18 19 20 21 22 23 24 25 26 27 28 29 ptd1/kbd1 ptd2/kbd2 ptd3/kbd3 30 31 32 64 17 48 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description data sheet mc68HC08KH12a ? rev. 1.0 24 general description motorola 1.5.2 52-pin low-profile quad flat pack (lqfp) figure 1-3 shows the 52-pin lqfp pin assignment. figure 1-3. 52-pin lqfp pin assignment (top view) dplus1 dplus0 vss2 ptb0 regout vssa osc2 osc1 cgmxfc vdda irq1 dminus0 dminus1 dplus2 dminus2 pta3 pta2 pta1 pta0 ptb3 ptb2 ptb1 ptd7/kbd7 ptd6/kbd6 ptd5/kbd5 ptd4/kbd4 ptd3/kbd3 vdd2 pta7 pta6 pta5 pta4 rst ptf0/kbf0 ptf1/kbf1 ptf2/kbf2 ptf3/kbf3 ptf4/kbf4 ptf5/kbf5 pte0/kbe0/tclk pte2/kbe2/tch1 pte1/kbe1/tch0 vss1 vdd1 ptc0 ptc1 ptc2 ptc3 ptc4 ptd0/kbd0 ptd1/kbd1 ptd2/kbd2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 39 38 37 36 35 34 33 32 31 30 29 28 27 52 51 50 49 48 47 46 45 44 43 42 41 40 pins not available on 52-pin lqfp package dplus3 ptb4 pte3/kbe3 dminus3 ptb5 pte4 dplus4 ptb6 ptf6/kbf6 dminus4 ptb7 ptf7/kbf7 note: these signal on the die are not conn ected to any pin (floating), therefore, user software should set these lines to output. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description pin assignments mc68HC08KH12a ? rev. 1.0 data sheet motorola general description 25 1.5.3 power supply pins (v dda , v ssa , v dd1 , v ss1 , v dd2 , and v ss2 ) v dda and v ssa are the analog power suppl y and ground pins used by the on-chip phase- locked loop circuit. v dd2 and v ss2 are the power supply and ground pins used by the internal circuitry of the chip. v dd1 and v ss1 are the power supply and gr ound pins to the i/o pads. the mcu operates from a single power supply. fast signal transitions on mcu pins place high, short-duration current demands on the power supply. to preven t noise problems, take special care to provide power suppl y bypassing at the mcu as figure 1-4 shows. place the bypass capacitors as close to the mcu power pins as possible. use high-frequency-res ponse ceramic capacitors for c bypass . c bulk are optional bulk current bypass ca pacitors for use in applications that require the port pins to source high current levels. figure 1-4. power supply bypassing mcu c bulk c bypass 10nf v ss1 + note: values shown are typical values. v dd2 c bypass 10nf v dd2 c bypass 10nf v ss2 v ssa v dda vbus f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description data sheet mc68HC08KH12a ? rev. 1.0 26 general description motorola 1.5.4 oscillator pins (osc1 and osc2) the osc1 and osc2 pins ar e the connections for the on-chip oscillator circuit. (see section 8. clock g enerator module (cgm) .) 1.5.5 external reset pin (rst ) a logic zero on the rst pin forces the mcu to a known start-up state. rst is bidirectional, allowin g a reset of the entire system. it is driven low when any internal reset s ource is asserted. the rst pin contains an internal pullup device. ( (see section 7. system integration module (sim) .) 1.5.6 external in terrupt pin (irq1 ) irq1 is an asynchronous external inte rrupt pin. this pi n contains an internal pullup device. (see section 14. external interrupt (irq) .) 1.5.7 usb data pins (dplus0?dplus4 and dminus0?dminus4) dplus0?dplus4 and dmin us0?dminus4 are t he differential data lines used by the usb module. (see section 9. universal serial bus module (usb) .) 1.5.8 voltage regul ator out (regout) regout is the 3.3v output of the on-chip voltage regulator. it is used to supply the voltage for the external pul lup resistor required by the usb on either dplus or dmin us lines, depending on type of usb function. regout is also used internally for the usb data dr iver and the phase- locked loop circuit. the regout pin requires an ex ternal bulk capacitor 1 f or larger and a bypass capacitor. (see section 9. universal serial bus module (usb) .) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description pin assignments mc68HC08KH12a ? rev. 1.0 data sheet motorola general description 27 1.5.9 port a input/out put (i/o) pins (pta7?pta0) pta7?pta0 are general-purpose bi directional i/o port pins. (see section 12. input/output (i/o) ports .) each pin contains a software configurable pull-up device when the pin is configured as an input. (see 12.9 port options .) 1.5.10 port b i /o pins (ptb7?ptb0) ptb7?ptb0 are general-purpose bi directional i/o port pins. (see section 12. input/output (i/o) ports .) each pin contains a software configurable pull-up device when the pin is configured as an input. (see 12.9 port options .) 1.5.11 port c i /o pins (ptc4?ptc0) ptc4?ptc0 are general-purpose bi directional i/o port pins. (see section 12. input/output (i/o) ports .) port c pins are software configurable to be led direct drive ports. each pin contains a software configurable pull-up device when the pin is configured as an input. (see 12.9 port options .) 1.5.12 port d i/o pi ns (ptd7/kbd7?ptd0/kbd0) ptd7/kbd7?ptd0/kbd0 are general- purpose bidirectional i/o port pins. (see section 12. input/o utput (i/o) ports .) any or all of the port d pins can be programmed to serv e as external interrupt pins. (see section 15. keyboard in terrupt module (kbi) .) 1.5.13 port e i/o pins (pte4, pte3/kbe3, pte2/kbe2/tch1, pte1/kbe1/tch0, pte0/kbe0/tclk) port-e is a 5-bit special function port which shares three of its pins with the timer interface module and four of its pins with keyboard interrupt module ( see section 12. input/o utput (i/o) ports , section 15. keyboard interrupt module (kbi) and section 11. timer interface module (tim) ). in addition, pte3-pte0 has built-in optical coupling f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description data sheet mc68HC08KH12a ? rev. 1.0 28 general description motorola interface for optical mouse application. (see section 12. input/output (i/o) ports .) 1.5.14 port f i/o pins (ptf7/kbf7?ptf0/kbf0) ptf7/kbf7?ptf0/kbf0 are gener al-purpose bidirectio nal i/o port pins. (see section 12. input/output (i/o) ports .) any or all of the port f pins can be programmed to serve as external interrupt pins. (see section 15. keyboard interrupt module (kbi) .) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC08KH12a ? rev. 1.0 data sheet motorola memory map 29 data sheet ? mc68HC08KH12a section 2. memory map 2.1 contents 2.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.3 i/o section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.4 monitor rom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 2.2 introduction the cpu08 can address 64 kbytes of memory space. the memory map, shown in figure 2-1 , includes: 11,776 bytes of rom 384 bytes of ram 26 bytes of user-defined vectors 240 bytes of monitor rom f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map data sheet mc68HC08KH12a ? rev. 1.0 30 memory map motorola $0000 $005f i/o registers (80 bytes) $0060 $01df ram (384 bytes) $01e0 $cdff unimplemented (52, 256 bytes) $d000 $fdff rom (11,776 bytes) $fe00 break status register (bsr) $fe01 reset status register (rsr) $fe02 reserved $fe03 break flag control register (bfcr) $fe04 interrupt status register 1 (int1) $fe05 interrupt status register 2 (int2) $fe06 reserved $fe07 reserved $fe08 $fe0b reserved (4 bytes) $fe0c break address high register (brkh) $fe0d break address low register (brkl) $fe0e break status and control register (bscr) $fe0f reserved $fe10 $feff monitor rom (240 bytes) $ff00 $ff00 to $ff8c unimplemented (141 bytes) $ff8d reserved $ffe5 $ff8e to $ffe5 unimplemented (88 bytes) $ffe6 $ffff vectors (26 bytes) figure 2-1. memory map f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map i/o section mc68HC08KH12a ? rev. 1.0 data sheet motorola memory map 31 2.3 i/o section addresses $0000?$005f, shown in figure 2-2 , contain most of the control, status, and data registers. additional i/o registers have the following addresses: $fe00 (break status register, bsr) $fe01 (reset status register, rsr) $fe02 (reserved) $fe03 (break flag co ntrol register, bfcr) $fe04 (interrupt status register 1, int1) $fe05 (interrupt status register 2, int2) $fe06 (reserved) $fe07 (reserved) $fe08 (reserved) $fe09 (reserved) $fe0a (reserved) $fe0b (reserved) $fe0c and $fe0d (br eak address register s, brkh and brkl) $fe0e (break status and control register, bscr) $ff8d (reserved) $ffff (cop contro l register, copctl) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map data sheet mc68HC08KH12a ? rev. 1.0 32 memory map motorola addr. name bit 7654321bit 0 $0000 port a data register (pta) r: pta7 pta6 pta5 pta4 pta3 pta2 pta1 pta0 w: $0001 port b data register (ptb) r: ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 w: $0002 port c data register (ptc) r:000 ptc4 ptc3 ptc2 ptc1 ptc0 w: $0003 port d data register (ptd) r: ptd7 ptd6 ptd5 ptd4 ptd3 ptd2 ptd1 ptd0 w: $0004 data direction register a (ddra) r: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 w: $0005 data direction register b (ddrb) r: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 w: $0006 data direction register c (ddrc) r:000 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 w: $0007 data direction register d (ddrd) r: ddrd7 ddrd6 ddrd5 ddrd4 ddrd3 ddrd2 ddrd1 ddrd0 w: $0008 port e data register (pte) r:000 pte4 pte3 pte2 pte1 pte0 w: $0009 port f data register (ptf) r: ptf7 ptf6 ptf5 ptf4 ptf3 ptf2 ptf1 ptf0 w: $000a data direction register e (ddre) r:000 ddre4 ddre3 ddre2 ddre1 ddre0 w: $000b data direction register f (ddrf) r: ddrf7 ddrf6 ddrf5 ddrf4 ddrf3 ddrf2 ddrf1 ddrf0 w: $000c port d keyboard status and control register (kbdscr) r:0000keydf0 imaskd moded w: ackd $000d port d keyboard interrupt enable register (kbdier) r: kbdie7 kbdie6 kbdie5 kbdie4 kbdie3 kbdie2 kbdie1 kbdie0 $000e port e keyboard status and control register (kbescr) r:0000 keyef 0 imaske modee w: acke $000f port e keyboard interrupt enable register (kbeier) r: pepe3 pepe2 pepe1 pepe0 kbeie3 kbeie2 kbeie1 kbeie0 w: = unimplemented r = reserved figure 2-2. control, stat us, and data registers f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map i/o section mc68HC08KH12a ? rev. 1.0 data sheet motorola memory map 33 $0010 tim status and control register (tsc) r: tof toie tstop 00 ps2 ps1 ps0 w: 0 trst $0011 unimplemented r: w: $0012 tim counter register high (tcnth) r: bit 15 14 13 12 11 10 9 bit 8 w: $0013 tim counter register low (tcntl) r:bit 7654321bit 0 w: $0014 tim counter modul o register high (tmodh) r: bit 15 14 13 12 11 10 9 bit 8 w: $0015 tim counter modulo register low (tmodl) r: bit 7654321bit 0 w: $0016 tim channel 0 status and control register (tsc0) r: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max w: 0 $0017 tim channel 0 register high (tch0h) r: bit 15 14 13 12 11 10 9 bit 8 w: $0018 tim channel 0 register low (tch0l) r: bit 7654321bit 0 w: $0019 tim channel 1 status and control register (tsc1) r: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max w: 0 $001a tim channel 1 register high (tch1h) r: bit 15 14 13 12 11 10 9 bit 8 $001b tim channel 1 register low (tch1l) r:bit 7654321bit 0 w: $001c port e optical interface enable register (eoier) r: yref2 yref1 yref0 xref2 xref1 xref0 oiey oiex w: $001d port option control register (poc) r: 0 0 ldd 00 pcp pbp pap w: $001e irq status and control register (iscr) r:0000irqf10 imask1 mode1 w ack1 $001f configuration register (config) ? r:0000 ssrec coprs stop copd w: ? one-time writable register addr. name bit 7654321bit 0 = unimplemented r = reserved figure 2-2. contro l, status, and data registers (continued) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map data sheet mc68HC08KH12a ? rev. 1.0 34 memory map motorola $0020 usb embedded device endpoint 0 data register 0 (de0d0) r: de0r07 de0r06 de0r05 de0r04 de0r03 de0r02 de0r01 de0r00 w: de0t07 de0t06 de0t05 de0t04 de0t03 de0t02 de0t01 de0t00 $0021 usb embedded device endpoint 0 data register 1 (de0d1) r: de0r17 de0r16 de0r15 de0r14 de0r13 de0r12 de0r11 de0r10 w: de0t17 de0t16 de0t15 de0t14 de0t13 de0t12 de0t11 de0t10 $0022 usb embedded device endpoint 0 data register 2 (de0d2) r: de0r27 de0r26 de0r25 de0r24 de0r23 de0r22 de0r21 de0r20 w: de0t27 de0t26 de0t25 de0t24 de0t23 de0t22 de0t21 de0t20 $0023 usb embedded device endpoint 0 data register 3 (de0d3) r: de0r37 de0r36 de0r35 de0r34 de0r33 de0r32 de0r31 de0r30 w: de0t37 de0t36 de0t35 de0t34 de0t33 de0t32 de0t31 de0t30 $0024 usb embedded device endpoint 0 data register 4 (de0d4) r: de0r47 de0r46 de0r45 de0r44 de0r43 de0r42 de0r41 de0r40 w: de0t47 de0t46 de0t45 de0t44 de0t43 de0t42 de0t41 de0t40 $0025 usb embedded device endpoint 0 data register 5 (de0d5) r: de0r57 de0r56 de0r55 de0r54 de0r53 de0r52 de0r51 de0r50 w: de0t57 de0t56 de0t55 de0t54 de0t53 de0t52 de0t51 de0t50 $0026 usb embedded device endpoint 0 data register 6 (de0d6) r: de0r67 de0r66 de0r65 de0r64 de0r63 de0r62 de0r61 de0r60 w: de0t67 de0t66 de0t65 de0t64 de0t63 de0t62 de0t61 de0t60 $0027 usb embedded device endpoint 0 data register 7 (de0d7) r: de0r77 de0r76 de0r75 de0r74 de0r73 de0r72 de0r71 de0r70 w: de0t77 de0t76 de0t75 de0t74 de0t73 de0t72 de0t71 de0t70 $0028 usb embedded device endpoint 1/2 data register 0 (de1d0) r: w: de1t07 de1t06 de1t05 de1t04 de1t03 de1t02 de1t01 de1t00 $0029 usb embedded device endpoint 1/2 data register 1 (de1d1) r: w: de1t17 de1t16 de1t15 de1t14 de1t13 de1t12 de1t11 de1t10 $002a usb embedded device endpoint 1/2 data register 2 (de1d2) r: w: de1t27 de1t26 de1t25 de1t24 de1t23 de1t22 de1t21 de1t20 $002b usb embedded device endpoint 1/2 data register 3 (de1d3) r: w: de1t37 de1t36 de1t35 de1t34 de1t33 de1t32 de1t31 de1t30 $002c usb embedded device endpoint 1/2 data register 4 (de1d4) r: w: de1t47 de1t46 de1t45 de1t44 de1t43 de1t42 de1t41 de1t40 $002d usb embedded device endpoint 1/2 data register 5 (de1d5) r: w: de1t57 de1t56 de1t55 de1t54 de1t53 de1t52 de1t51 de1t50 $002e usb embedded device endpoint 1/2 data register 6 (de1d6) r: w: de1t67 de1t66 de1t65 de1t64 de1t63 de1t62 de1t61 de1t60 $002f usb embedded device endpoint 1/2 data register 7 (de1d7) r: w: de1t77 de1t76 de1t75 de1t74 de1t73 de1t72 de1t71 de1t70 addr. name bit 7654321bit 0 = unimplemented r = reserved figure 2-2. contro l, status, and data registers (continued) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map i/o section mc68HC08KH12a ? rev. 1.0 data sheet motorola memory map 35 $0030 usb hub endpoint 0 data register 0 (he0d0) r: he0r07 he0r06 he0r05 he0r04 he0r03 he0r02 he0r01 he0r00 w: he0t07 he0t06 he0t05 he0t04 he0t03 he0t02 he0t01 he0t00 $0031 usb hub endpoint 0 data register 1 (he0d1) r: he0r17 he0r16 he0r15 he0r14 he0r13 he0r12 he0r11 he0r10 w: he0t17 he0t16 he0t15 he0t14 he0t13 he0t12 he0t11 he0t10 $0032 usb hub endpoint 0 data register 2 (he0d2) r: he0r27 he0r26 he0r25 he0r24 he0r23 he0r22 he0r21 he0r20 w: he0t27 he0t26 he0t25 he0t24 he0t23 he0t22 he0t21 he0t20 $0033 usb hub endpoint 0 data register 3 (he0d3) r: he0r37 he0r36 he0r35 he0r34 he0r33 he0r32 he0r31 he0r30 w: he0t37 he0t36 he0t35 he0t34 he0t33 he0t32 he0t31 he0t30 $0034 usb hub endpoint 0 data register 4 (he0d4) r: he0r47 he0r46 he0r45 he0r44 he0r43 he0r42 he0r41 he0r40 w: he0t47 he0t46 he0t45 he0t44 he0t43 he0t42 he0t41 he0t40 $0035 usb hub endpoint 0 data register 5 (he0d5) r: he0r57 he0r56 he0r55 he0r54 he0r53 he0r52 he0r51 he0r50 w: he0t57 he0t56 he0t55 he0t54 he0t53 he0t52 he0t51 he0t50 $0036 usb hub endpoint 0 data register 6 (he0d6) r: he0r67 he0r66 he0r65 he0r64 he0r63 he0r62 he0r61 he0r60 w: he0t67 he0t66 he0t65 he0t64 he0t63 he0t62 he0t61 he0t60 $0037 usb hub endpoint 0 data register 7 (he0d7) r: he0r77 he0r76 he0r75 he0r74 he0r73 he0r72 he0r71 he0r70 w: he0t77 he0t76 he0t75 he0t74 he0t73 he0t72 he0t71 he0t70 $0038 unimplemented r: w: $0039 unimplemented r: w: $003a pll control register (pctl) r: pllie pllf pllon bcs pre1 pre0 0 0 w: $003b pll bandwidth control register (pbwc) r: auto lock acq 00000 w: $003c pll multiplier select register high (pmsh) r: mul11 mul10 mul9 mul8 w: $003d pll multiplier select register low (pmsl) r: mul7 mul6 mul5 mul4 mul3 mul2 mul1 mul0 w: $003e unimplemented r: w: $003f pll reference divider select register (prds) r: rds3 rds2 rds1 rds0 w: addr. name bit 7654321bit 0 = unimplemented r = reserved figure 2-2. contro l, status, and data registers (continued) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map data sheet mc68HC08KH12a ? rev. 1.0 36 memory map motorola $0040 port f keyboard status and control register (kbfscr) r:0000 keyff 0 imaskf modef w: ackf $0041 port f keyboard interrupt enable register (kbfier) r: kbfie7 kbfie6 kbfie5 kbfie4 kbfie3 kbfie2 kbfie1 kbfie0 w: $0042 port f pull-up enable register (pfper) r: pfpe7 pfpe6 pfpe5 pfpe4 pfpe3 pfpe2 pfpe1 pfpe0 w: $0043 unimplemented r: w: $0044 unimplemented r: w: $0045 unimplemented r: w: $0046 unimplemented r: w: $0047 usb embedded device control register 2 (dcr2) r:0000 enable2 enable1 dstall2 dstall1 w: $0048 usb embedded device address register (daddr) r: deven dadd6 dadd5 dadd4 dadd3 dadd2 dadd1 dadd0 w: $0049 usb embedded device interrupt register 0 (dir0) r: txd0f rxd0f 0 0 txd0ie rxd0ie 00 w: txd0fr rxd0fr $004a usb embedded device interrupt register 1 (dir1) r: txd1f 0 0 0 txd1ie 000 w: txd1fr $004b usb embedded device control register 0 (dcr0) r: t0seq dstall0 tx0e rx0e tp0siz3 tp0siz2 tp0siz1 tp0siz0 w: $004c usb embedded device control register 1 (dcr1) r: t1seq endadd tx1e 0 tp1siz3 tp1siz2 tp1siz1 tp1siz0 w: $004d usb embedded device status register (dsr) r: drseq dsetup dtx1st 0 rp0siz3 rp0siz2 rp0siz1 rp0siz0 w: dtx1str $004e unimplemented r: w: $004f unimplemented r: w: addr. name bit 7654321bit 0 = unimplemented r = reserved figure 2-2. contro l, status, and data registers (continued) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map i/o section mc68HC08KH12a ? rev. 1.0 data sheet motorola memory map 37 $0050 unimplemented r: w: $0051 usb hub downstream port 1 control register (hdp1cr) r: pen1 lowsp1 rst1 resum1 susp1 0d1+d1? w: $0052 usb hub downstream port 2 control register (hdp2cr) r: pen2 lowsp2 rst2 resum2 susp2 0d2+d2? w: $0053 usb hub downstream port 3 control register (hdp3cr) r: pen3 lowsp3 rst3 resum3 susp3 0d3+d3? w: $0054 usb hub downstream port 4 control register (hdp4cr) r: pen4 lowsp4 rst4 resum4 susp4 0d4+d4? w: $0055 unimplemented r: w: $0056 usb sie timing interrupt register (sietir) r: soff eof2f eopf tranf sofie eof2ie eopie tranie w: $0057 usb sie timing status register (sietsr) r:rstf0lockf00000 w: rstfr lockfr soffr eof2fr eopfr tranfr $0058 usb hub address register (haddr) r: usben add6 add5 add4 add3 add2 add1 add0 w: $0059 usb hub interrupt register 0 (hir0) r: txdf rxdf 0 0 txdie rxdie 00 w: txdfr rxdfr $005a unimplemented r: w: $005b usb hub control register 0 (hcr0) r: tseq stall0 txe rxe tpsiz3 tpsiz2 tpsiz1 tpsiz0 w: $005c usb hub endpoint1 control & data register (hcdr) r: stall1 pnew pchg5 pchg4 pchg3 pchg2 pchg1 pchg0 w: $005d usb hub status register (hsr) r: rseq setup tx1st 0 rpsiz3 rpsiz2 rpsiz1 rpsiz0 w: tx1str $005e usb hub root port control register (hrpcr) r:000 resum0 suspnd 0d0+d0? w: $005f unimplemented r: w: addr. name bit 7654321bit 0 = unimplemented r = reserved figure 2-2. contro l, status, and data registers (continued) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map data sheet mc68HC08KH12a ? rev. 1.0 38 memory map motorola $fe00 break status register (bsr) r: rrrrrr sbsw r w: $fe01 reset status register (rsr) r: por pin cop ilop ilad usb 0 0 w: $fe02 reserved r: w: $fe03 break flag control register (bfcr) r: bcferrrrrrr w: $fe04 interrupt status register 1 (int1) r: if6 if5 if4 if3 if2 if1 0 0 w:rrrrrrrr $fe05 interrupt status register 2 (int2) r: 0 0 0 if11 if10 if9 if8 if7 w:rrrrrrrr $fe06 reserved r: w: $fe07 reserved r: w: $fe08 unimplemented r: w: $fe09 unimplemented r: w: $fe0a unimplemented r: w: $fe0b unimplemented r: w: $fe0c break address register high (brkh) r: bit 15 14 13 12 11 10 9 bit 8 w: $fe0d break address register low (brkl) r: bit 7654321bit 0 w: $fe0e break status and control register (brkscr) r: brke brka 000000 w: $ff8d reserved r: w: $ffff cop control register (copctl) r: low byte of reset vector w: writing clears cop counter (any value) addr. name bit 7654321bit 0 = unimplemented r = reserved figure 2-2. contro l, status, and data registers (continued) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map monitor rom mc68HC08KH12a ? rev. 1.0 data sheet motorola memory map 39 table 2-1 is a list of vector locations. 2.4 monitor rom the 240 bytes at addresses $fe 10?$feff are reserved rom addresses that contain the instruct ions for the monitor functions. (see section 10. monitor rom (mon) .) table 2-1. vector addresses address vector $ffe6 pll vector (high) $ffe7 pll vector (low) $ffe8 port-f keyboard vector (high) $ffe9 port-f keyboard vector (low) $ffea port-d keyboard vector (high) $ffeb port-d keyboard vector (low) $ffec port-e keyboard vector (high) $ffed port-e keyboard vector (low) $ffee tim overflow vector (high) $ffef tim overflow vector (low) $fff0 tim channel 1 vector (high) $fff1 tim channel 1 vector (low) $fff2 tim channel 0 vector (high) $fff3 tim channel 0 vector (low) $fff4 usb device endpoint interrupt vector (high) $fff5 usb device endpoint interrupt vector (low) $fff6 usb hub endpoint in terrupt vector (high) $fff7 usb hub endpoint interrupt vector (low) $fff8 usb sie timing interrupt vector (high) $fff9 usb sie timing interrupt vector (low) $fffa irq1 vector (high) $fffb irq1 vector (low) $fffc swi vector (high) $fffd swi vector (low) $fffe reset vector (high) $ffff reset vector (low) priority low high f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map data sheet mc68HC08KH12a ? rev. 1.0 40 memory map motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC08KH12a ? rev. 1.0 data sheet motorola random-access memory (ram) 41 data sheet ? mc68HC08KH12a section 3. random-access memory (ram) 3.1 contents 3.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 3.2 introduction this section describes the 384 bytes of ram. 3.3 functional description addresses $0060 through $01 df are ram locations. the location of the stack ram is programmable. the 16-bit stack pointer allows the stack to be anywhere in the 64-kbyte memory space. note: for correct operation, the stack pointer must point only to ram locations. within page zero are 160 bytes of ra m. because the location of the stack ram is programmable, all page zero ram locations can be used for i/o control and user data or code. when the stack pointer is moved from its reset location at $00ff, dire ct addressing mode instructions can access efficiently all page zero ram locations. pa ge zero ram, therefore, provides ideal locati ons for frequently accessed global variables. before processing an interrupt, the cp u uses five bytes of the stack to save the contents of the cpu registers. note: for m6805 compatibility, the h register is not stacked. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . random-access memory (ram) data sheet mc68HC08KH12a ? rev. 1.0 42 random-access memory (ram) motorola during a subroutine call, the cpu uses two bytes of the stack to store the return address. the stack po inter decrements during pushes and increments during pulls. note: be careful when using nested subr outines. the cpu ma y overwrite data in the ram during a s ubroutine or during the interrupt stacking operation. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC08KH12a ? rev. 1.0 data sheet motorola read-only memory (rom) 43 data sheet ? mc68HC08KH12a section 4. read-only memory (rom) 4.1 contents 4.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 4.2 introduction this section describes th e 11,776 bytes of read-only memory (rom) and 26 bytes of user vectors, avai lable on the mc68HC08KH12a device (rom part). 4.3 functional description these addresses are user rom locations: $d000 ? $fdff $ffe6 ? $ffff (these locati ons are reserved for user-defined interrupt and reset vectors.) note: a security feature prevents viewing of t he rom contents. 1 1. no security feature is absolutely secure. howe ver, motorola?s strategy is to make reading or copying the rom contents difficult for unauthorized users. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . read-only memory (rom) data sheet mc68HC08KH12a ? rev. 1.0 44 read-only memory (rom) motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC08KH12a ? rev. 1.0 data sheet motorola configuration register (config) 45 data sheet ? mc68HC08KH12a section 5. configurat ion register (config) 5.1 contents 5.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 5.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 5.2 introduction this section describes the config uration register (config). the configuration register enables or disables the following options: stop mode recovery time (32 cgmxclk cycles or 4096 cgmxclk cycles) stop instruction computer operating pr operly module (cop) cop reset period (coprs), (2 13 ?2 4 ) cgmxclk or (2 18 ?2 4 ) cgmxclk 5.3 functional description the configuration register is used in the initialization of various options. the configuration register can be wri tten once after each reset. all of the configuration register bits are clea red during reset. since the various options affect the operat ion of the mcu it is recommended that this register be written immedi ately after reset. the conf iguration register is located at $001f. the configuration register may be read at anytime. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . configuration register (config) data sheet mc68HC08KH12a ? rev. 1.0 46 configuration regist er (config) motorola note: the config register is a special r egister containing one-time writable latches after each reset. upon a reset, the config register defaults to the predetermined settin gs as shown in figure 5-1 . ssrec ? short stop recovery bit ssrec enables the cp u to exit stop mode with a delay of 32 cgmxclk cycles instead of a 4096 cgmxclk cycle delay. 1 = stop mode recovery after 32 cgmxclk cycles 0 = stop mode recovery after 4096 cgmxclk cycles note: exiting stop mode by pulling reset will result in the long stop recovery. if using an external crystal , do not set t he ssrec bit. coprs ? cop reset pe riod selection bit 1 = cop reset cycle is (2 13 ?2 4 ) cgmxclk 0 = cop reset cycle is (2 18 ?2 4 ) cgmxclk stop ? stop instruction enable bit stop enables the stop instruction. 1 = stop inst ruction enabled 0 = stop instruction tr eated as illegal opcode copd ? cop disable bit copd disables the cop module. see section 13. computer operating properly (cop) . 1 = cop module disabled 0 = cop module enabled address: $001f bit 7654321bit 0 read: 0000 ssrec coprs stop copd write: reset:00000000 = unimplemented figure 5-1. configurat ion register (config) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC08KH12a ? rev. 1.0 data sheet motorola central processor unit (cpu) 47 data sheet ? mc68HC08KH12a section 6. central processor unit (cpu) 6.1 contents 6.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.4 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.4.1 accumulator (a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.4.2 index register (h:x). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.4.3 stack pointer (sp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.4.4 program counter (pc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.4.5 condition code register (ccr) . . . . . . . . . . . . . . . . . . . . . . 53 6.5 arithmetic/logic unit (alu) . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.2 introduction this section describes the central pr ocessor unit. the m68hc08 cpu is an enhanced and fully object-code-compat ible version of the m68hc05 cpu. the cpu08 reference manual (motorola document number cpu08rm/ad) contains a description of the cpu instruction set, addressing modes, and architecture. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) data sheet mc68HC08KH12a ? rev. 1.0 48 central processor unit (cpu) motorola 6.3 features features of the cpu include the following: full upward, object-code com patibility with m68hc05 family 16-bit stack pointer with st ack manipulation instructions 16-bit index register with x-register m anipulation instructions 6-mhz cpu internal bus frequency 64-kbyte program/data memory space 16 addressing modes memory-to-memory data move s without using accumulator fast 8-bit by 8-bit multiply and 16-bit by 8-bit di vide instructions enhanced binary-coded deci mal (bcd) data handling modular architecture with expanda ble internal bus definition for extension of addressi ng range beyond 64 kbytes low-power stop and wait modes 6.4 cpu registers figure 6-1 shows the five cpu registers. cpu regist ers are not part of the memory map. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) cpu registers mc68HC08KH12a ? rev. 1.0 data sheet motorola central processor unit (cpu) 49 figure 6-1. cpu registers 6.4.1 accumulator (a) the accumulator is a general-purpose 8- bit register. the cpu uses the accumulator to hold operands and th e results of arithmetic/logic operations. accumulator (a) index register (h:x) stack pointer (sp) program counter (pc) condition code register (ccr) carry/borrow flag zero flag negative flag interrupt mask half-carry flag two?s complement overflow flag v11hinzc h x 0 0 0 0 7 15 15 15 70 bit 7654321bit 0 read: write: reset: unaffected by reset figure 6-2. accumulator (a) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) data sheet mc68HC08KH12a ? rev. 1.0 50 central processor unit (cpu) motorola 6.4.2 index register (h:x) the 16-bit index register allows indexed addressing of a 64-kbyte memory space. h is the upper byte of the index regi ster, and x is the lower byte. h:x is the conc atenated 16-bit index register. in the indexed addressi ng modes, the cpu uses the contents of the index register to determine the conditional addr ess of the operand. the index register can serve also as a temporary data storage location. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 bit 0 read: write: reset:0 0 0 0 0 0 0 0xxxxxxxx x = indeterminate figure 6-3. index register (h:x) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) cpu registers mc68HC08KH12a ? rev. 1.0 data sheet motorola central processor unit (cpu) 51 6.4.3 stack pointer (sp) the stack pointer is a 16-bi t register that contains the address of the next location on the stack. during a rese t, the stack pointer is preset to $00ff. the reset stack pointer (rsp) in struction also sets the least significant byte to $ff but does not af fect the most significant byte. the stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack. in the stack pointer 8-bi t offset and 16-bit offs et addressing modes, the stack pointer can functi on as an index register to access data on the stack. the cpu uses the contents of the stack pointer to determine the conditional address of the operand. note: the location of the stack is arbitr ary and may be relocated anywhere in ram. moving the sp out of page zero ($0000 to $00ff) frees direct address (page zero) space. for correct operation, the stack pointer must point only to ram locations. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 bit 0 read: write: reset:0000000011111111 figure 6-4. stack pointer (sp) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) data sheet mc68HC08KH12a ? rev. 1.0 52 central processor unit (cpu) motorola 6.4.4 program counter (pc) the program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched. normally, the program counter autom atically increm ents to the next sequential memory location every time an instruct ion or operand is fetched. jump, branch, and interr upt operations l oad the program counter with an addr ess other than that of the next sequential location. during reset, the program counter is loaded with the reset vector address located at $fffe and $ffff. the vect or address is the address of the first instruction to be executed after exiti ng the reset state. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 bit 0 read: write: reset: loaded with vector from $fffe and $ffff figure 6-5. prog ram counter (pc) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) cpu registers mc68HC08KH12a ? rev. 1.0 data sheet motorola central processor unit (cpu) 53 6.4.5 condition code register (ccr) the 8-bit condition code register cont ains the interrupt mask and five flags that indicate the re sults of the instruction just executed. bits 6 and 5 are set permanently to logic one. the following pa ragraphs describe the functions of the c ondition code register. v ? overflow flag the cpu sets the overfl ow flag when a two's complement overflow occurs. the signed branch instructions bgt, bge, ble, and blt use the overflow flag. 1 = overflow 0 = no overflow h ? half-carry flag the cpu sets the half-carry fl ag when a carry occurs between accumulator bits 3 and 4 during an add or adc o peration. the half- carry flag is required for binary- coded decimal (bcd ) arithmetic operations. the daa instru ction uses the states of the h and c flags to determine the appropriate correction factor. 1 = carry between bits 3 and 4 0 = no carry between bits 3 and 4 bit 76 5 4 3 2 1bit 0 read: v11hinzc write: reset:x11x1xxx x = indeterminate figure 6-6. condition code register (ccr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) data sheet mc68HC08KH12a ? rev. 1.0 54 central processor unit (cpu) motorola i ? interrupt mask when the interrupt mask is set, all maskable cpu interrupts are disabled. cpu interrupts are ena bled when the interrupt mask is cleared. when a cpu in terrupt occurs, the interrupt mask is set automatically after t he cpu registers are sa ved on the stack, but before the interrupt vector is fetched. 1 = interrupts disabled 0 = interrupts enabled note: to maintain m6805 compatibility, the upper byte of the i ndex register (h) is not stacked automatical ly. if the interrupt serv ice routine modifies h, then the user must st ack and unstack h using the pshh and pulh instructions. after the i bit is clear ed, the highest-priority interrupt request is serviced first. a return from interrupt (rti) instru ction pulls the cp u registers from the stack and restores the interr upt mask from the stack. after any reset, the interrupt mask is set and can only be cleared by the clear interrupt mask software instruction (cli). n ? negative flag the cpu sets the negative flag when an arithmet ic operation, logic operation, or data manipul ation produces a negative result, setting bit 7 of the result. 1 = negative result 0 = non-negative result z ? zero flag the cpu sets the zero flag when an arithmetic operation, logic operation, or data manipulati on produces a result of $00. 1 = zero result 0 = non-zero result f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) arithmetic/logic unit (alu) mc68HC08KH12a ? rev. 1.0 data sheet motorola central processor unit (cpu) 55 c ? carry/borrow flag the cpu sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of th e accumulator or when a subtraction operation requires a borrow. some instructions ? such as bit test and branch, shift, and rotate ? also clear or set the carry/borrow flag. 1 = carry out of bit 7 0 = no carry out of bit 7 6.5 arithmetic/logic unit (alu) the alu performs the arit hmetic and logic operat ions defined by the instruction set. refer to the cpu08 reference manual (motorola document number cpu08rm/ad) for a description of the instructions and addressing modes and more detail about cpu architecture. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processor unit (cpu) data sheet mc68HC08KH12a ? rev. 1.0 56 central processor unit (cpu) motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC08KH12a ? rev. 1.0 data sheet motorola system integration module (sim) 57 data sheet ? mc68HC08KH12a section 7. system integration module (sim) 7.1 contents 7.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 7.3 sim bus clock control and generation . . . . . . . . . . . . . . . . . . 61 7.3.1 bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 7.3.2 clock start-up from por . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 7.3.3 clocks in stop mode and wait mode . . . . . . . . . . . . . . . . . . 62 7.4 reset and system initializa tion. . . . . . . . . . . . . . . . . . . . . . . . . 62 7.4.1 external pin reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 7.4.2 active resets from inte rnal sources . . . . . . . . . . . . . . . . . . 63 7.4.2.1 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 7.4.2.2 computer operati ng properly (cop) reset. . . . . . . . . . . 65 7.4.2.3 illegal opcode reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 7.4.2.4 illegal address reset . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 7.4.2.5 universal serial bu s reset . . . . . . . . . . . . . . . . . . . . . . . 66 7.5 sim counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 7.5.1 sim counter during power-on rese t . . . . . . . . . . . . . . . . . 67 7.5.2 sim counter during stop mode reco very . . . . . . . . . . . . . . 67 7.5.3 sim counter and reset st ates. . . . . . . . . . . . . . . . . . . . . . . 67 7.6 exception control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 7.6.1 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 7.6.1.1 hardware interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 7.6.1.2 swi instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 7.6.2 interrupt status regist ers. . . . . . . . . . . . . . . . . . . . . . . . . . . 72 7.6.2.1 interrupt stat us register 1 . . . . . . . . . . . . . . . . . . . . . . . . 73 7.6.2.2 interrupt stat us register 2 . . . . . . . . . . . . . . . . . . . . . . . . 74 7.6.2.3 interrupt stat us register 3 . . . . . . . . . . . . . . . . . . . . . . . . 74 7.6.3 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 7.6.4 break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 7.6.5 status flag protection in break mode . . . . . . . . . . . . . . . . . 75 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) data sheet mc68HC08KH12a ? rev. 1.0 58 system integration module (sim) motorola 7.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 7.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 7.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 7.8 sim registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 7.8.1 break status register (bsr) . . . . . . . . . . . . . . . . . . . . . . . .79 7.8.2 reset status register (rsr) . . . . . . . . . . . . . . . . . . . . . . . . 80 7.8.3 break flag control register (bfcr) . . . . . . . . . . . . . . . . . . 81 7.2 introduction this section describes the system integration module (sim), which supports up to 24 external and/or inte rnal interrupts. together with the cpu, the sim controls all mcu activi ties. a block diagram of the sim is shown in figure 7-1 . figure 7-2 is a summary of the sim i/o registers. the sim is a system state controller t hat coordinates cpu and exception timing. the sim is responsible for: bus clock generation and cont rol for cpu and peripherals ? top/wait/reset/break entry and recovery ? internal clock control master reset control, includi ng power-on reset (por) and cop timeout interrupt control: ? acknowledge timing ? arbitration control timing ? vector address generation cpu enable/disable timing modular architecture exp andable to 128 interrupt sources f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) introduction mc68HC08KH12a ? rev. 1.0 data sheet motorola system integration module (sim) 59 figure 7-1. sim block diagram stop/wait clock control clock generators por control reset pin control sim reset status register interrupt control and priority decode module stop module wait cpu stop (from cpu) cpu wait (from cpu) simoscen (to cgm) cgmout (from cgm) internal clocks master reset control reset pin logic illegal opcode (from cpu) illegal address (from address map decoders) cop timeout (from cop module) interrupt sources cpu interface reset control sim counter cop clock cgmxclk (from cgm) 2 usb reset (from usb module) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) data sheet mc68HC08KH12a ? rev. 1.0 60 system integration module (sim) motorola addr. register name bit 7654321bit 0 $fe00 break status register (bsr) read: rrrrrr sbsw r write: reset: 0 $fe01 reset status register (rsr) read: por pin cop ilop ilad usb 0 0 write: reset:10000000 $fe03 break flag control register (bfcr) read: bcferrrrrrr write: reset: 0 $fe04 interrupt status register 1 (int1) read: if6 if5 if4 if3 if2 if1 0 0 write:rrrrrrrr reset:00000000 $fe05 interrupt status register 2 (int2) read: 0 0 0 if11 if10 if9 if8 if7 write:rrrrrrrr reset:00000000 $fe06 interrupt status register 3 (int3) read: 00000000 write:rrrrrrrr reset:00000000 = unimplemented r = reserved for factory test figure 7-2. sim i/o register summary f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) sim bus clock control and generation mc68HC08KH12a ? rev. 1.0 data sheet motorola system integration module (sim) 61 table 7-1 shows the internal signal names used in this section. 7.3 sim bus clock control and generation the bus clock generator provides system clock signal s for the cpu and peripherals on the mcu. the syst em clocks are generated from an incoming clock, cg mout, as shown in figure 7-3 . figure 7-3. sim clock signals 7.3.1 bus timing in user mode , the internal bus frequency is the o scillator frequency (cgmxclk) divi ded by four. table 7-1. signal name conventions signal name description cgmxclk buffered osc1 from the oscillator cgmout the cgmxclk frequency divided by two. this signal is again divided by two in the sim to generate the internal bus clocks (bus clock = cgmxclk divided by four) iab internal address bus idb internal data bus porrst signal from the power-on reset module to the sim irst internal reset signal r/w read/write signal 2 bus clock generators sim sim counter from pll/oscillator from pll/oscillator cgmout cgmxclk f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) data sheet mc68HC08KH12a ? rev. 1.0 62 system integration module (sim) motorola 7.3.2 clock start-up from por when the power-on reset module generat es a reset, t he clocks to the cpu and peripherals are inactive an d held in an inactive phase until after the 4096 cgmxclk cycle por tim eout has completed. the rst pin is driven low by the sim du ring this entire period. the ibus clocks start upon completion of the timeout. 7.3.3 clocks in st op mode and wait mode upon exit from stop mode by an interr upt, break, or rese t, the sim allows cgmxclk to clock the sim coun ter. the cpu and peripheral clocks do not become active until after the stop delay timeout. this timeout is selectable as 4096 or 32 cgmxclk cycles. (see 7.7.2 stop mode .) in wait mode, t he cpu clocks are inactive. th e sim also produces two sets of clocks for other modules. refer to the wait mode subsection of each module to see if t he module is active or i nactive in wait mode. some modules can be programmed to be active in wait mode. 7.4 reset and system initialization the mcu has these reset sources: power-on reset module (por) external reset pin (rst ) computer operating pr operly module (cop) illegal opcode illegal address universal serial bus module (usb) all of these resets produce the vector $fffe?ffff ($fefe?feff in monitor mode) and assert the internal reset signal (irst). irst causes all registers to be returned to thei r default values and all modules to be returned to thei r reset states. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) reset and system initialization mc68HC08KH12a ? rev. 1.0 data sheet motorola system integration module (sim) 63 an internal reset cl ears the sim counter (see 7.5 sim counter ), but an external reset does not. each of th e resets sets a co rresponding bit in the reset status register (rsr). (see 7.8 sim registers .) 7.4.1 external pin reset the rst pin circuits incl ude an internal pullup device. pulling the asynchronous rst pin low halts all processing. the pin bit of the reset status register (rsr) is set as long as rst is held low for a minimum of 67 cgmxclk cycles, assuming that t he por was not the source of the reset. see table 7-2 for details. figure 7-4 shows the relative timing. figure 7-4. extern al reset timing 7.4.2 active resets from internal sources all internal reset sources actively pull the rst pin low for 32 cgmxclk cycles to allow resetting of external peripherals. the inte rnal reset signal irst continues to be assert ed for an additional 32 cycles. see figure 7- 5 . an internal reset can be caused by an illegal addres s, illegal opcode, cop timeout, or por. (see figure 7-6. sourc es of internal reset .) note that for por resets, the sim cycles through 4096 cgmxclk cycles during which the sim forces the rst pin low. the internal reset signal then follows the sequence from the falling edge of rst shown in figure 7-5 . table 7-2. pin bit set timing reset type number of cycles required to set pin por 4163 (4096 + 64 + 3) all others 67 (64 + 3) rst iab pc vect h vect l cgmout f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) data sheet mc68HC08KH12a ? rev. 1.0 64 system integration module (sim) motorola figure 7-5. inter nal reset timing the cop reset is asynchro nous to the bus clock. figure 7-6. sources of internal reset the active reset feature allows the par t to issue a reset to peripherals and other chips within a system built around the mcu. 7.4.2.1 power-on reset when power is first applied to the mcu, the power-on reset module (por) generates a pul se to indicate that pow er-on has occurred. the external reset pin (rst ) is held low while the sim counter counts out 4096 cgmxclk cycles. sixty-four cg mxclk cycles later, the cpu and memories are released from reset to allow the reset vector sequence to occur. at power-on, t he following events occur: a por pulse is generated. the internal reset signal is asserted. the sim enables the oscill ator to drive cgmxclk. internal clocks to the cpu and m odules are held i nactive for 4096 cgmxclk cycles to al low stabilization of the oscillator. the rst pin is driven low during th e oscillator stabilization time. the por bit of the reset status re gister (rsr) is set and all other bits in the register are cleared. irst rst rst pulled low by mcu iab 32 cycles 32 cycles vector high cgmxclk illegal address rst illegal opcode rst coprst por internal reset usb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) reset and system initialization mc68HC08KH12a ? rev. 1.0 data sheet motorola system integration module (sim) 65 figure 7-7. por recovery 7.4.2.2 computer operat ing properly (cop) reset an input to the sim is reserved for the cop reset signal. the overflow of the cop counter causes an internal reset and sets the cop bit in the reset status register (rsr). th e sim actively pulls down the rst pin for all internal reset sources. to prevent a cop module timeout, wr ite any value to location $ffff. writing to location $ffff clears the cop counter and stages 12 through 5 of the sim counter. the sim counter output, which occurs at least every 2 12 ? 2 4 cgmxclk cycles, drives the cop counter. the cop should be serviced as s oon as possible out of reset to guarantee the maximum amount of time before the first timeout. the cop module is disabled if the rst pin or the irq1 /v pp pin is held at v dd +v hi while the mcu is in moni tor mode. the cop module can be disabled only through co mbinational logic condi tioned with the high voltage signal on the rst or the irq1 /v pp pin. this prevents the cop from becoming disabled as a result of external noise. during a break state, v dd +v hi on the rst pin disables the cop module. porrst osc1 cgmxclk cgmout rst iab 4096 cycles 32 cycles 32 cycles $fffe $ffff f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) data sheet mc68HC08KH12a ? rev. 1.0 66 system integration module (sim) motorola 7.4.2.3 illegal opcode reset the sim decodes signals from the cpu to detect illegal instructions. an illegal instruction sets t he ilop bit in the reset st atus register (rsr) and causes a reset. if the stop enable bit, st op, in the mask option regi ster is logic zero, the sim treats the stop instruction as an illegal opcode and causes an illegal opcode reset. the sim actively pulls down the rst pin for all internal reset sources. 7.4.2.4 illegal address reset an opcode fetch from an unm apped address genera tes an illegal address reset. the sim ve rifies that t he cpu is fetching an opcode prior to asserting the ilad bit in the reset stat us register (rsr) and resetting the mcu. a data fetch from an unmapped addre ss does not generate a reset. the sim active ly pulls down the rst pin for all internal reset sources. 7.4.2.5 universal serial bus reset the usb module will detect a reset sign al on the bus by the presence of an extended se0 at the usb data pins of the upstream port. the reset signaling is specified to be present for a minimum of 10 ms. an active device (powered and not in the su spend state) seeing a single-ended zero on its usb data inputs for more than 2.5 s may treat that signal as a reset, but must have interpreted the signaling as a reset within 5.5 s. for usb device, an se0 condition between 4 and 8 low speed bit times or 32 and 64 high s peed bit times represents a va lid usb reset. after the reset is removed, the device will be in the attac hed, but not yet addressed or configured state (ref er to section 9.1 of the usb specification). the device must be able to accept device address via a set_address command (refer to secti on 9.4 of the usb specification) no later than 10 ms after the reset is removed. reset can wake a device from the suspended mode. a de vice may take up to 10 ms to wake up from the suspended state. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) sim counter mc68HC08KH12a ? rev. 1.0 data sheet motorola system integration module (sim) 67 7.5 sim counter the sim counter is used by the pow er-on reset module (por) and in stop mode recovery to allow the os cillator time to stabilize before enabling the internal bus (i bus) clocks. the sim c ounter also serves as a prescalar for the computer operati ng properly module (cop). the sim counter uses 12 stages for counting, followed by a 13th stage that triggers a reset of sim counters and supplies the cl ock for the cop module. the sim counter is clo cked by the falli ng edge of cgmxclk. 7.5.1 sim counter during power-on reset the power-on reset module (por) dete cts power appli ed to the mcu. at power-on, the por ci rcuit asserts the signal porrst. once the sim is initialized, it enables the oscillator to drive the bus clock state machine. 7.5.2 sim counter du ring stop mode recovery the sim counter also is used for stop mode recovery. the stop instruction clears the sim counter. af ter an interrupt, brea k, or reset, the sim senses the state of the short st op recovery bit, ssrec, in the mask option register. if the s srec bit is a logic one, t hen the stop recovery is reduced from the normal delay of 4096 cgmxcl k cycles down to 32 cgmxclk cycles. this is ideal for ap plications using canned oscillators that do not require long start-up times from st op mode. external crystal applications should use the full stop recovery time, that is, with ssrec cleared in the configurat ion register (config). 7.5.3 sim counter and reset states external reset has no effect on the sim counter. ( see 7.7.2 stop mode for details.) the sim counter is fr ee-running after all reset states. ( see 7.4.2 active resets from internal sources for counter control and internal reset re covery sequences.) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) data sheet mc68HC08KH12a ? rev. 1.0 68 system integration module (sim) motorola 7.6 exception control normal, sequential progra m execution can be chang ed in three different ways: interrupts ? maskable hardware cpu interrupts ? non-maskable software interrupt instruction (swi) reset break interrupts 7.6.1 interrupts an interrupt temporarily changes th e sequence of program execution to respond to a parti cular event. figure 7-8 flow charts the handling of system interrupts. interrupts are latched, and arbitration is performed in the sim at the start of interrupt processing. the arbitration result is a constant that the cpu uses to determine which ve ctor to fetch. once an interrupt is latched by the sim, no other interrupt can take precedence, regardless of priority, until the latched interrupt is serv iced (or the i bit is cleared). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) exception control mc68HC08KH12a ? rev. 1.0 data sheet motorola system integration module (sim) 69 figure 7-8. interrupt processing no no no yes no no yes no yes yes from reset break i bit set? irq1 interrupt? usb interrupt? fetch next instruction unstack cpu registers. stack cpu registers set i bit load pc with interrupt vector execute instruction. yes yes i bit set? interrupt? yes other interrupts? no swi instruciton? rti instruciton? f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) data sheet mc68HC08KH12a ? rev. 1.0 70 system integration module (sim) motorola at the beginning of an interrupt, the cpu sa ves the cpu register contents on the sta ck and sets the interrupt ma sk (i bit) to prevent additional interrupts. at the end of an interrupt , the rti instruction recovers the cpu regist er contents from the stack so that normal processing can resume. figure 7-9 shows interrupt entry timing. figure 7-10 shows interrupt recovery timing. figure 7-9 . interrupt entry figure 7-10. in terrupt recovery 7.6.1.1 hardwa re interrupts a hardware interrupt does not stop the current in struction. processing of a hardware interrupt begins after completion of t he current instruction. when the current instruction is complete, the sim checks all pending hardware interrupts. if interrupts ar e not masked (i bit clear in the condition code register), and if the corres ponding interrupt enable bit is module idb r/w interrupt dummy sp sp ? 1 sp ? 2 sp ? 3 sp ? 4 vect h vect l start addr iab dummy pc ? 1[7:0] pc ? 1[15:8] x a ccr v data h v data l opcode i bit module idb r/w interrupt sp ? 4 sp ? 3 sp ? 2 sp ? 1 sp pc pc + 1 iab ccr a x pc ? 1[7:0] pc ? 1[15:8] opcode operand i bit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) exception control mc68HC08KH12a ? rev. 1.0 data sheet motorola system integration module (sim) 71 set, the sim proceeds with interrup t processing; other wise, the next instruction is fetched and executed. if more than one interrupt is pending at th e end of an instruction execution, the highest priority interrupt is serviced first. figure 7-11 demonstrates what hap pens when two interrupts are pending. if an interrupt is pending upon exit from the original inte rrupt service routine, the pending interrupt is serviced before the lda in struction is executed. figure 7-11 . interrupt recognition example the lda opcode is pr efetched by both th e int1 and int2 rti instructions. however, in the case of the int1 rti prefetch, this is a redundant operation. note: to maintain compatibility with the m6805 family, the h register is not pushed on the stack during in terrupt entry. if the in terrupt service routine modifies the h register or uses the indexed addressing mode, software should save the h register and then restore it prio r to exiting the routine. cli lda int1 pulh rti int2 background routine #$ff pshh int1 interrupt service routine pulh rti pshh int2 interrupt service routine f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) data sheet mc68HC08KH12a ? rev. 1.0 72 system integration module (sim) motorola 7.6.1.2 swi instruction the swi instruction is a non-maskable instruct ion that causes an interrupt regardless of the state of the interrupt mask (i bit) in the condition code register. note: a software interrupt pushes pc onto the stack. a software interrupt does not push pc ? 1, as a hardware interrupt does. 7.6.2 interrupt status registers the flags in the interrupt status re gisters identify maskable interrupt sources. table 7-3 summarizes the interrupt sources and the interrupt status register flags that they set. the interrupt status registers can be useful for debugging. table 7-3. interrupt sources source flag mask (1) int register flag priority (2) vector address swi instruction ? 0 $fffc?$fffd irq1 pin irqf1 imask1 if1 1 $fffa?$fffb hub start of frame interrupt soff sofie if2 2 $fff8?$fff9 hub 2nd end of frame point interrupt eof2f eof2ie hub end of packet interrupt eopf eopie hub bus signal transition detect interrupt tranf tranie hub endpoint0 transmit interrupt txdf txdie if3 3 $fff6?$fff7 hub endpoint0 receive interrupt rxdf rxdie device endpoint 0 transmit interrupt txd0f txd0ie if4 4 $fff4?$fff5 device endpoint 0 receive interrupt rxd0f rxd0ie usb endpoint1/2 transmit interrupt txd1f txd1ie tim channel 0 ch0f ch0ie if5 5 $fff2?$fff3 tim channel 1 ch1f ch1ie if6 6 $fff0?$fff1 tim overflow tof toie if7 7 $ffee?$ffef port-e keyboard pin interr upt keyef imaske if8 8 $ffec?$ffed f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) exception control mc68HC08KH12a ? rev. 1.0 data sheet motorola system integration module (sim) 73 7.6.2.1 interrupt status register 1 i f 6?i f 1 ? interrupt flags 1?6 these flags indicate the presence of interrupt r equests from the sources shown in table 7-3 . 1 = interrupt request present 0 = no interrupt request present bit 0 and bit 1 ? always read 0 port-d keyboard pin interr upt keydf imaskd if9 9 $ffea?$ffeb port-f keyboard pin interrup t keyff imaskf if10 10 $ffe8?$ffe9 phase-locked loop interrupt pllf pllie if11 11 $ffe6?$ffe7 (1) the i bit in the condition code register is a global mask for all interrupts sources except the swi instruction. (2) 0= highest priority table 7-3. interrupt sources source flag mask (1) int register flag priority (2) vector address address: $fe04 bit 7654321bit 0 read: if6 if5 if4 if3 if2 if1 0 0 write:rrrrrrrr reset:00000000 r= reserved figure 7-12. interrupt st atus register 1 (int1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) data sheet mc68HC08KH12a ? rev. 1.0 74 system integration module (sim) motorola 7.6.2.2 interrupt status register 2 i f 11?i f 7 ? interrupt flags 11?7 these flags indicate the presence of interrupt r equests from the sources shown in table 7-3 . 1 = interrupt request present 0 = no interrupt request present 7.6.2.3 interrupt status register 3 bits 7?0 ? always read 0 address: $fe05 bit 7654321bit 0 read: 0 0 0 if11 if10 if9 if8 if7 write:rrrrrrrr reset:00000000 r= reserved figure 7-13. interrupt st atus register 2 (int2) address: $fe06 bit 7654321bit 0 read: 00000000 write:rrrrrrrr reset:00000000 r= reserved figure 7-14. interrupt st atus register 2 (int2) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) low-power modes mc68HC08KH12a ? rev. 1.0 data sheet motorola system integration module (sim) 75 7.6.3 reset all reset sources always have equal and highest pr iority and cannot be arbitrated. 7.6.4 break interrupts the break module can st op normal program flow at a software- programmable break point by assert ing its break interrupt output. (see section 16. break module (brk) .) the sim puts the cpu into the break state by forcing it to the swi vector loca tion. refer to the break interrupt subsection of each module to see how each module is affected by the break state. 7.6.5 status flag pr otection in break mode the sim controls whether status fl ags contained in ot her modules can be cleared during break m ode. the user can sele ct whether flags are protected from being clea red by properly initiali zing the break clear flag enable bit (bcfe) in the break flag contro l register (bfcr). protecting flags in break mode ensures that set flags will not be cleared while in break mode. this protection allows registers to be freely read and written during break mo de without losing stat us flag information. setting the bcfe bit e nables the clearing mechani sms. once cleared in break mode, a flag remains cleared even when break mode is exited. status flags with a two-step cleari ng mechanism ? for example, a read of one register followed by the read or write of another ? are protected, even when the first step is accomplished prior to entering break mode. upon leaving break mode, execution of the second step will clear the flag as normal. 7.7 low-power modes executing the wait or stop instruction puts t he mcu in a low-power- consumption mode for st andby situations. the s im holds the cpu in a non-clocked state. the operation of eac h of these mode s is described f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) data sheet mc68HC08KH12a ? rev. 1.0 76 system integration module (sim) motorola below. both stop and wait clear the interrupt mask (i) in the condition code register, allowing interrupts to occur. 7.7.1 wait mode in wait mode, t he cpu clocks are inactive while the peripheral clocks continue to run. figure 7-15 shows the timing fo r wait mode entry. a module that is active during wa it mode can wake up the cpu with an interrupt if the interrupt is enabled . stacking for the interrupt begins one cycle after the wait instruction duri ng which the interr upt occurred. in wait mode, the cpu clocks are i nactive. refer to the wait mode subsection of each module to see if th e module is active or inactive in wait mode. some modules can be programmed to be active in wait mode. wait mode can also be exited by a reset or break. a break interrupt during wait mode sets the sim break stop/wait bit, sbsw , in the break status register (bsr). if the cop disable bit, co pd, in the mask option register is logic zero , then the computer oper ating properly module (cop) is enabled and remains active in wait mode. figure 7-15. wait mode entry timing figure 7-16 and figure 7-17 show the timing for wait recovery. wait addr + 1 same same iab idb previous data next opcode same wait addr same r/w note: previous data can be operand data or the wait opcode, depending on the last instruction. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) low-power modes mc68HC08KH12a ? rev. 1.0 data sheet motorola system integration module (sim) 77 figure 7-16. wait recovery from interrupt or break figure 7-17. wait recover y from internal reset 7.7.2 stop mode in stop mode, the sim counter is reset and the system clocks are disabled. an interrupt request from a module can cause an exit from stop mode. stacking for inte rrupts begins after the selected stop recovery time has elapsed. reset or break al so causes an exit from stop mode. the sim disables the oscillator si gnals (cgmout and cgmxclk) in stop mode, stopping the cpu and peripherals. stop recovery time is selectable using the ssrec bit in the configurati on register (config). if ssrec is set, stop recovery is r educed from the nor mal delay of 4096 cgmxclk cycles down to 32. this is ideal for applications using canned oscillators that do not require lo ng startup time s from stop mode. note: external crystal applicati ons should use the full stop recovery time by clearing the ssrec bit. $6e0c $6e0b $00ff $00fe $00fd $00fc $a6 $a6 $01 $0b $6e $a6 iab idb exitstopwait note: exitstopwait = rst pin or cpu interrupt or break interrupt iab idb rst $a6 $a6 $6e0b rst vct h rst vct l $a6 cgmxclkcgmxclk 32 cycles 32 cycles f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) data sheet mc68HC08KH12a ? rev. 1.0 78 system integration module (sim) motorola a break interrupt during stop mode sets the si m break stop/wait bit (sbsw) in the break st atus register (bsr). the sim counter is held in reset from the execution of the stop instruction until th e beginning of stop recovery. it is then used to time the recovery period. figure 7-18 shows stop mode entry timing. note: to minimize stop current, all pins configured as i nputs should be driven to a logic 1 or logic 0. figure 7-18. stop mode entry timing figure 7-19. stop mode recovery from interrupt or break stop addr + 1 same same iab idb previous data next opcode same stop addr same r/w cpustop note: previous data can be operand data or the stop opcode, depending on the last instruction. cgmxclk int/break iab stop + 2 stop + 2 sp sp ? 1 sp ? 2 sp ? 3 stop +1 stop recovery period f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) sim registers mc68HC08KH12a ? rev. 1.0 data sheet motorola system integration module (sim) 79 7.8 sim registers the sim has three memo ry mapped registers. table 7-4 shows the mapping of thes e registers. 7.8.1 break status register (bsr) the break status register contains a flag to indicate that a break caused an exit from stop or wait mode. sbsw ? sim break stop/wait this status bit is useful in applic ations requiring a return to wait or stop mode after exiting from a break interrupt. clear sbsw by writing a logic zero to it. reset clears sbsw. 1 = stop mode or wait mode wa s exited by break interrupt 0 = stop mode or wait mode was not exited by break interrupt sbsw can be read within the break state swi r outine. the user can modify the return address on the st ack by subtractin g one from it. the following code is an example of this. writing zero to the sbsw bit clears it. table 7-4. sim registers address register access mode $fe00 bsr user $fe01 rsr user $fe03 bfcr user address: $fe00 bit 7654321bit 0 read: rrrrrr sbsw r write: note 1 reset: 0 r = reserved 1. writing a logic zero clears sbsw figure 7-20. break stat us register (bsr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) data sheet mc68HC08KH12a ? rev. 1.0 80 system integration module (sim) motorola 7.8.2 reset stat us register (rsr) this register contains six flags that show the sour ce of the last reset. clear the sim reset status register by reading it. a power-on reset sets the por bit and clear s all other bits in the register. ; ; ; this code works if the h register has been pushed onto the stack in the break service routine software. this code should be executed at the end of the break service routine software. hibyte equ 5 lobyte equ 6 ; if not sbsw, do rti brclr sbsw,bsr, return ; ; see if wait mode or stop mode was exited by break tst lobyte,sp ; if returnlo is not zero, bne dolo ; then just decrement low byte. dec hibyte,sp ; else deal with high byte, too. dolo dec lobyte,sp ; point to wait/stop opcode. return pulh rti ; restore h register. address: $fe01 bit 7654321bit 0 read: por pin cop ilop ilad usb 0 0 write: por:10000000 = unimplemented figure 7-21. reset st atus register (rsr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) sim registers mc68HC08KH12a ? rev. 1.0 data sheet motorola system integration module (sim) 81 por ? power-on reset bit 1 = last reset caused by por circuit 0 = read of rsr pin ? external reset bit 1 = last reset caused by external reset pin (rst ) 0 = por or read of rsr cop ? computer operati ng properly reset bit 1 = last reset caused by cop counter 0 = por or read of rsr ilop ? illegal opcode reset bit 1 = last reset caused by an illegal opcode 0 = por or read of rsr ilad ? illegal address reset bit (opcode fetches only) 1 = last reset caused by an opc ode fetch from an illegal address 0 = por or read of rsr usb ?universal serial bus reset bit 1 = last reset caused by an usb module 0 = por or read of rsr 7.8.3 break flag cont rol register (bfcr) the break control register contains a bit that enables so ftware to clear status bits while the mc u is in a break state. address: $fe03 bit 7654321bit 0 read: bcferrrrrrr write: reset:00000000 r= reserved figure 7-22. break flag c ontrol register (bfcr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . system integration module (sim) data sheet mc68HC08KH12a ? rev. 1.0 82 system integration module (sim) motorola bcfe ? break clear flag enable bit this read/write bit enables software to clear status bits by accessing status registers while the mcu is in a break state. to clear status bits during the br eak state, the bcfe bit must be set. 1 = status bits clearable during break 0 = status bits not clearable during break f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC08KH12a ? rev. 1.0 data sheet motorola clock generator module (cgm) 83 data sheet ? mc68HC08KH12a section 8. clock generator module (cgm) 8.1 contents 8.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 8.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 8.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 8.4.1 crystal oscillator circui t . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 8.4.2 phase-locked loop circ uit (pll) . . . . . . . . . . . . . . . . . . . . 87 8.4.3 pll circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 8.4.4 acquisition and tracking modes . . . . . . . . . . . . . . . . . . . . . 89 8.4.5 manual and automati c pll bandwidth modes. . . . . . . . . . . 89 8.4.6 programming the pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 8.4.7 special program ming exceptions . . . . . . . . . . . . . . . . . . . . 91 8.4.8 base clock selector circ uit . . . . . . . . . . . . . . . . . . . . . . . . . 92 8.4.9 cgm external connectio ns . . . . . . . . . . . . . . . . . . . . . . . . . 92 8.5 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 8.5.1 crystal amplifier input pin (osc1). . . . . . . . . . . . . . . . . . . . 94 8.5.2 crystal amplifier out put pin (osc2) . . . . . . . . . . . . . . . . . . 94 8.5.3 external filter capac itor pin (cgmxfc) . . . . . . . . . . . . . . . 94 8.5.4 pll analog power pin (v dda ) . . . . . . . . . . . . . . . . . . . . . . . 94 8.5.5 pll anal og ground pin (v ssa ) . . . . . . . . . . . . . . . . . . . . . . 94 8.5.6 buffered crystal clock output (c gmvout) . . . . . . . . . . . . 95 8.5.7 cgmvsel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 8.5.8 oscillator enable signal (simoscen). . . . . . . . . . . . . . . . . 95 8.5.9 crystal output frequency signal (cgmxclk) . . . . . . . . . . 95 8.5.10 cgm base clock out put (cgmout). . . . . . . . . . . . . . . . . . 95 8.5.11 cgm cpu interrupt (cgm int) . . . . . . . . . . . . . . . . . . . . . . 95 8.6 cgm registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 8.6.1 pll control register (pctl) . . . . . . . . . . . . . . . . . . . . . . . . 98 8.6.2 pll bandwidth control register (pbwc) . . . . . . . . . . . . . 100 8.6.3 pll multiplier select regist ers (pmsh:pmsl) . . . . . . . . . 101 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) data sheet mc68HC08KH12a ? rev. 1.0 84 clock generator module (cgm) motorola 8.6.4 pll referenc e divider select register (prds) . . . . . . . . 102 8.7 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 8.8 special modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 8.8.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 8.8.2 cgm during break inte rrupts. . . . . . . . . . . . . . . . . . . . . . . 104 8.9 acquisition/lock time spec ifications . . . . . . . . . . . . . . . . . . . 104 8.9.1 acquisition/lock time definitions. . . . . . . . . . . . . . . . . . . .104 8.9.2 parametric influences on reaction time . . . . . . . . . . . . . . 105 8.9.3 choosing a filter capac itor . . . . . . . . . . . . . . . . . . . . . . . . 107 8.9.4 reaction time calculat ion . . . . . . . . . . . . . . . . . . . . . . . . . 107 8.2 introduction this section describes the clock generator module (cgm). the cgm generates the crystal clo ck signal, cgmxclk, wh ich operates at the frequency of the crystal. the cgm also generates the base clock signal, cgmout, which is based on either t he crystal clock divided by two or the phase-locked loop (pll) clock, cgmpclk, divi ded by two. this is the clock from which t he sim derives the system clocks, including the bus clock, which is at a frequen cy of cgmout/2. the pll also generates a cgmvclk clock, at 48m hz, for use as the usbclk. the pll is a fully functional freque ncy generator de signed for use with crystals or ceramic resonators. this cgm is optimized to generate a 48mhz refe rence frequency for the usb module, from a 6mhz crystal. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) features mc68HC08KH12a ? rev. 1.0 data sheet motorola clock generator module (cgm) 85 8.3 features features of the cgm include: vco center-of-range frequency tuned to 48mhz for low-jitter clock reference for usb module low-frequency crystal operation with low-power operation and high-output frequen cy resolution programmable reference divider for even greater resolution programmable prescaler for po wer-of-two increases in bus frequency automatic bandwidth control mode for low-jitt er operation automatic frequency lock detector cpu interrupt on entry or exit from locked condition 8.4 functional description the cgm consists of three major submodules: crystal oscillator circuit ? the crystal osc illator circuit generates the constant crystal frequency clock, cgmxclk. phase-locked l oop (pll) ? the p ll generates the programmable vco frequency cl ock, cgmvclk and cgmpclk. base clock selector circuit ? th is software-controlled circuit selects either cgmx clk divided by two or the pll clock, cgmpclk, divided by two as t he base clock, cgmout. the sim derives the system clocks from cgmout. figure 8-1 shows the struct ure of the cgm. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) data sheet mc68HC08KH12a ? rev. 1.0 86 clock generator module (cgm) motorola figure 8-1. cgm block diagram bcs phase detector loop filter frequency divider voltage controlled oscillator automatic mode control lock detector clock cgmxclk cgmout cgmvdv cgmvclk simoscen interrupt control cgmint cgmrdv pll analog 2 cgmrclk osc2 osc1 select circuit v dda cgmxfc v ssa lock auto acq pllie pllf mul[11:0] reference divider rds[3:0] frequency divider pre[1:0] cgmpclk usbclk p n r clock select circuit phase-locked loop (pll) oscillator (osc) 48mhz f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) functional description mc68HC08KH12a ? rev. 1.0 data sheet motorola clock generator module (cgm) 87 8.4.1 crystal os cillator circuit the crystal oscillator circuit consis ts of an inverting amplifier and an external crystal. the osc1 pin is t he input to the amp lifier and the osc2 pin is the output. the simoscen si gnal from the sys tem integration module (sim) enables the cr ystal oscillator circuit. the cgmxclk signal is t he output of the crystal oscillator circuit and runs at a rate equal to the crystal frequency. cg mxclk is then buffered to produce cgmrclk, t he pll reference clock. cgmxclk can be used by other modul es which require precise timing for operation. the duty cycl e of cgmxclk is not guaranteed to be 50% and depends on external factors, including t he crystal and related external components. an externally generated clock also can feed the osc1 pin of the crystal oscillator ci rcuit. connect the external clock to the osc1 pin and let the osc2 pin float. 8.4.2 phase-locked loop circuit (pll) the pll is a frequency gene rator that can operate in either acquisition mode or tracking mode, depending on the a ccuracy of the output frequency. the pll can change betw een acquisition and tracking modes either automat ically or manually. 8.4.3 pll circuits the pll consists of these circuits: voltage-controlled oscillator (vco) reference divider frequency prescaler modulo vco fr equency divider phase detector loop filter lock detector f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) data sheet mc68HC08KH12a ? rev. 1.0 88 clock generator module (cgm) motorola the operating range of the vco is programmable for a wide range of frequencies and for maximum immunity to external noise, including supply and cgm/xfc noise. the vc o frequency is bo und to a range from roughly 40mh z to 56mhz, f vrs . modulating the voltage on the cgm/xfc pin changes the frequency within this range. by design, f vrs is tuned to a nominal cent er-of-range frequency of 48mhz. cgmrclk is the pll reference clock, a buffered versio n of cgmxclk. cgmrclk runs at a frequency, f rclk , and is fed to the pll through a programmable modulo referenc e divider, which divides f rclk by a factor r. this feature allows frequency steps of higher resolution. the divider?s output is the final reference clo ck, cgmrdv, runni ng at a frequency f rdv =f rclk /r. the vco?s output clock, clk, running at a frequency f vclk is fed back through a programmable prescale divider and a pr ogrammable modulo divider. the prescaler divides the vc o clock by a power-of-two factor p and the modulo divi der reduces the vco clo ck by a factor, n. the dividers? output is the vco feedba ck clock, cgmvdv, running at a frequency f vdv =f vclk /(n 2 p ). (see 8.4.6 programming the pll for more information.) the phase detector then compares th e vco feedback clock, cgmvdv, with the final reference clock, cgmrdv. a correction pulse is generated based on the phase di fference between the two si gnals. the loop filter then slightly alters t he dc voltage on the external capacitor connected to cgm/xfc based on t he width and direction of the correction pulse. the filter can make fa st or slow correcti ons depending on its mode, described in 8.4.4 acquisiti on and tracking modes . the value of the external capacitor and the refer ence frequency determines the speed of the corrections and the stability of the pll. the lock detector compares the freque ncies of the vco feedback clock, cgmvdv, and the final reference clock, cgmrdv. therefore, the speed of the lock detector is directly proportional to t he final reference frequency, f rdv . the circuit determines the mo de of the pll and the lock condition based on this comparison. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) functional description mc68HC08KH12a ? rev. 1.0 data sheet motorola clock generator module (cgm) 89 8.4.4 acquisition and tracking modes the pll filter is manually or automatically conf igurable into one of two operating modes: acquisition mode ? in acquisition m ode, the filter can make large frequency corrections to the vc o. this mode is used at pll startup or when the pll has su ffered a severe noise hit and the vco frequency is far off t he desired frequency. when in acquisition mode, the acq bit is clear in the pll bandwidth control register. (see 8.6.2 pll bandwidth c ontrol register (pbwc) .) tracking mode ? in tracking mode , the filter makes only small corrections to the frequency of t he vco. pll jitter is much lower in tracking mode, but the response to noise is also slower. the pll enters tracking mode wh en the vco frequency is nearly correct, such as when the pll is selected as the base clock source. (see 8.4.8 base clock se lector circuit .) the pll is automatically in tracking mode wh en not in acqui sition mode or when the acq bit is set. 8.4.5 manual and automa tic pll bandwidth modes this cgm is optimized fo r automatic pll bandwid th mode, and is the mode recommended for most users. in automatic bandwidth control mode (auto=1) , the lock detector automatically switches between acquisition and tracking modes. automatic bandwidth c ontrol mode also is us ed to determi ne when the vco clock, cgmvclk, is safe to us e as the source for the base clock, cgmout. (see 8.6.2 pll bandwidth c ontrol register (pbwc) .) if pll interrupts are enabled, the soft ware can wait for a pll interrupt request and then check the lock bit. if interrupts ar e disabled, software can poll the lock bit continuously (d uring pll startup, usually) or at periodic intervals. in ei ther case, w hen the lock bit is set, the vco clock is safe to use as the so urce for the base clock. (see 8.4.8 base clock selector circuit .) if the vco is select ed as the source for the base clock and the lock bit is clear , the pll has suffered a severe noise hit and th e software must take a ppropriate action, depending on f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) data sheet mc68HC08KH12a ? rev. 1.0 90 clock generator module (cgm) motorola the application. (see 8.7 interrupts for information and precautions on using interrupts.) the following c onditions apply when the pll is in automatic bandwidth control mode: the acq bit (see 8.6.2 pll bandwidth control register (pbwc) .) is a read-only indi cator of the mode of the filter. (see 8.4.4 acquisition and tracking modes .) the acq bit is set when the vco fr equency is within a certain tolerance, ? trk , and is cleared when the vco frequency is out of a certain tolerance, ? unt . (see 8.9 acquisition/lock time specifications for more information.) the lock bit is a read-only indica tor of the locked state of the pll. the lock bit is set when the vco frequency is within a certain tolerance, ? lock , and is cleared when the vco frequency is out of a certain tolerance ? unl . (see 8.9 acquisition/lock time specifications for more information.) cpu interrupts can occur if enabl ed (pllie = 1) when the pll?s lock condition changes, toggli ng the lock bit. (see 8.6.1 pll control register (pctl) .) 8.4.6 programming the pll the following procedure shows how to progr am the pll. 1. choose the desired bus frequency, f bus . the relationship between the vco frequency f vclk and the bus frequency f bus is the vco frequency need to be at 48mhz fo r the usb module reference clock. choose p = 0, 1, 2, or 3 fo r a bus frequency of 12mhz, 6mhz, 3mhz, or 1.5mhz respectively. f vclk 2 p ------------- 4f bus = 48mhz 2 p ------------------- - 4f bus = f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) functional description mc68HC08KH12a ? rev. 1.0 data sheet motorola clock generator module (cgm) 91 2. choose a practical pll (cr ystal) reference frequency, f rclk , and the reference clock divider, r. frequency errors to the pll are corrected at a rate of f rclk /r. for stability and lock time reduction, this rate must be as fast as possible. the vco frequency must be an integer multiple of this rate. the relationship bet ween the vco frequency f vclk and the reference frequency f rclk is choose the reference divider r = 1 for fast lo ck. choose a f rclk frequency with an int eger divisor of f bus and solve for n. 3. program the pll r egisters accordingly: a. in the pre bits of the pll control r egister (pctl), program the binary equi valent of p. b. in the pll multiplier select re gister low (pms l) and the pll multiplier select register hi gh (pmsh), progr am the binary equivalent of n. c. in the pll reference divider se lect register (prds), program the binary coded eq uivalent of r. table 8-1 provides a numeric example (numbers are in hexadecimal notation): 8.4.7 special programming exceptions the programming method described in 8.4.6 programming the pll does not account for three possible exce ptions. a value of zero for r, n, or l is meaningless when used in th e equations given. to account for these exceptions: table 8-1. cgm numeric example f bus f rclk pnr 6mhz 6mhz 1 004 1 f vclk 2 p n r ---------------- - f rclk () = hence: 48mhz 2 p n r ---------------- - f rclk () = f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) data sheet mc68HC08KH12a ? rev. 1.0 92 clock generator module (cgm) motorola a zero value for r or n is interpreted exactly the same as a value of one. a zero value for l disabl es the pll and prevents its selection as the source for the base clock. (see 8.4.8 base clock selector circuit .) 8.4.8 base clock se lector circuit this circuit is used to select either the crystal clock, cgmxclk, or the pll clock, cgmpclk, as the sour ce of the base clock, cgmout. the two input clocks go thro ugh a transition control ci rcuit that waits up to three cgmxclk cycles and three cg mpclk cycles to change from one clock source to the other. duri ng this time, cgmout is held in stasis. the output of the transition co ntrol circuit is then divided by two to correct the duty cycle. therefore, the bus clo ck frequency, which is one-half of the base clock frequency, is one-fourth the frequency of the selected clock (cgmxclk or cgmpclk). the bcs bit in the pll cont rol register (pctl) sele cts which clock drives cgmout. the vco clock c annot be selected as t he base clock source if the pll is not turned on. the pll cannot be turned off if the vco clock is selected. the pll cannot be tur ned on or off simultaneously with the selection or deselection of the vco clock. this circuit is also used to select ei ther the crystal cl ock, cgmxclk or the vco clock, cgmvclk, as the source of the usb clock, usbclk. 8.4.9 cgm exte rnal connections in its typical confi guration, the cgm requ ires seven external components. five of thes e are for the crystal o scillator and two are for the pll. the crystal oscillator is normally connected in a pierce oscillator configuration, as shown in figure 8-2 . figure 8-2 shows only the logical representation of the internal components and ma y not represent actual circuitry. the oscillator conf iguration uses five components: crystal, x 1 fixed capacitor, c 1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) functional description mc68HC08KH12a ? rev. 1.0 data sheet motorola clock generator module (cgm) 93 tuning capacitor, c 2 (can also be a fixed capacitor) feedback resistor, r b series resistor, r s (optional) the series resistor (r s ) is included in the diagram to follow strict pierce oscillator guidelines and may not be r equired for all rang es of operation, especially with high frequency cryst als. refer to the crystal manufacturer?s data for more information. figure 8-2 also shows the exter nal components for the pll: bypass capacitor, c byp filter capacitor, c f routing should be done with great care to mini mize signal cross talk and noise. see section 17. electri cal specifications for capacitor and resistor values. figure 8-2. cgm external connections simoscen cgmxclk r b x 1 *r s can be zero (shorted) when us ed with higher-frequency crystals . refer to manufacturer?s data. osc1 osc2 v ssa cgmxfc v dda v dd c byp r s * c 1 c 2 c f f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) data sheet mc68HC08KH12a ? rev. 1.0 94 clock generator module (cgm) motorola 8.5 i/o signals the following paragraphs descr ibe the cgm i/o signals. 8.5.1 crystal amplifi er input pin (osc1) the osc1 pin is an input to the crystal oscillator amplifier. 8.5.2 crystal amplifi er output pin (osc2) the osc2 pin is the output of the crystal oscillator inverting amplifier. 8.5.3 external filter capacitor pin (cgmxfc) the cgmxfc pin is required by the loop filter to fi lter out phase corrections. a small external capac itor is connected to this pin. note: to prevent noise problems, c f should be placed as close to the cgmxfc pin as possible, with minimum routing distances and no routing of other si gnals across the c f connection. 8.5.4 pll analog power pin (v dda ) v dda is a power pin used by the analog portions of the p ll. connect the v dda pin to the same vo ltage potential as the v dd pin. note: route v dda carefully for maximum noise immunity and place bypass capacitors as close as possible to the package. 8.5.5 pll analog ground pin (v ssa ) v ssa is a ground pin used by the analog portions of the pll. connect the v ssa pin to the same volt age potential as the v ss pin. note: route v ssa carefully for maximum noise immunity and place bypass capacitors as close as possible to the package. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) i/o signals mc68HC08KH12a ? rev. 1.0 data sheet motorola clock generator module (cgm) 95 8.5.6 buffered crystal clock output (cgmvout) cgmvout buffers the osc1 clock for external use. 8.5.7 cgmvsel cgmvsel must be ti ed low or floated. 8.5.8 oscillator e nable signal (simoscen) the simoscen signal come s from the system int egration module (sim) and enables the osci llator and pll. 8.5.9 crystal output frequency signal (cgmxclk) cgmxclk is the crystal o scillator output signal. it runs at the full speed of the crystal (f xclk ) and comes directly from the crystal oscillator circuit. figure 8-2 shows only the logical relati on of cgmxclk to osc1 and osc2 and may not represent the actual circuitry. the duty cycle of cgmxclk is unknown and may depend on the crystal and other external factors. also, the frequen cy and amplitude of cgmxclk can be unstable at startup. 8.5.10 cgm base cl ock output (cgmout) cgmout is the clock output of the cgm. this signal goes to the sim, which generates the mcu clocks. cg mout is a 50 percent duty cycle clock running at twice the bus frequency. cgmout is software programmable to be eith er the oscillator outpu t, cgmxclk, divided by two or the vco clock, cgmvclk, divided by two. 8.5.11 cgm cpu interrupt (cgmint) cgmint is the interrupt signal generated by the pll lock detector. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) data sheet mc68HC08KH12a ? rev. 1.0 96 clock generator module (cgm) motorola 8.6 cgm registers these registers control and m onitor operation of the cgm: pll control regi ster (pctl) (see 8.6.1 pll control register (pctl) .) pll bandwidth control register (pbwc) (see 8.6.2 pll bandwidth control register (pbwc) .) pll multiplier select registers (pmsh:pmsl) (see 8.6.3 pll multiplier select r egisters (pmsh:pmsl) .) pll reference divider sele ct register (prds) (see 8.6.4 pll reference divider sele ct register (prds) .) table 8-2 is a summary of the cgm registers. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) cgm registers mc68HC08KH12a ? rev. 1.0 data sheet motorola clock generator module (cgm) 97 table 8-2. cgm i/o register summary addr. register name bit 7654321bit 0 $003a pll control register (pctl) read: pllie pllf pllon bcs pre1 pre2 00 write: reset:00101000 $003b pll bandwidth control register (pbwc) read: auto lock acq 00000 write: reset:00000000 $003c pll multiplier select register high (pmsh) read: 0000 mul11 mul10 mul9 mul8 write: reset:00000000 $003d pll multiplier select register low (pmsl) read: mul7 mul6 mul5 mul4 mul3 mul2 mul1 mul0 write: reset:00000010 $003e unimplemented read: write: reset: $003f pll reference divider select register (prds) read: 0000 rds3 rds2 rds1 rds0 write: reset:00000001 = unimplemented notes: 1. when auto = 0, pllie is forced clear and is read-only. 2. when auto = 0, pllf and lock read as clear. 3. when auto = 1, acq is read-only. 4. when pllon = 0 or vrs7:vrs0 = $0, bcs is forced clear and is read-only. 5. when pllon = 1, the pll programming register is read-only. 6. when bcs = 1, pllon is forced set and is read-only. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) data sheet mc68HC08KH12a ? rev. 1.0 98 clock generator module (cgm) motorola 8.6.1 pll contro l register (pctl) the pll control register contains t he interrupt enable a nd flag bits, the on/off switch, the base clock selector bit, the prescaler bits, and the vco power of two range selector bits. pllie ? pll interrupt enable bit this read/write bi t enables the pll to gener ate an interrupt request when the lock bit toggles, sett ing the pll flag, pllf. when the auto bit in the pll bandwidth c ontrol register (pbwc) is clear, pllie cannot be written and reads as logic zero. reset clears the pllie bit. 1 = pll interrupts enabled 0 = pll interrupts disabled pllf ? pll interrupt flag bit this read-only bit is set wheneve r the lock bit toggles. pllf generates an interrupt request if th e pllie bit also is set. pllf always reads as logic zero when t he auto bit in the pll bandwidth control register (pbwc) is clear . clear the pllf bi t by reading the pll control register. re set clears the pllf bit. 1 = change in lock condition 0 = no change in lock condition note: do not inadvertently cl ear the pllf bit. any re ad or read-modify-write operation on the pll control regi ster clears the pllf bit. address: $003a bit 7654321bit 0 read: pllie pllf pllon bcs pre1 pre2 00 write: reset:00101000 = unimplemented figure 8-3. pll cont rol register (pctl) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) cgm registers mc68HC08KH12a ? rev. 1.0 data sheet motorola clock generator module (cgm) 99 pllon ? pll on bit this read/write bit activates t he pll and enables the vco clock, cgmvclk. pllon cannot be cleared if the vco clock is driving the base clock, cgmout (bcs = 1). (see 8.4.8 base clock selector circuit .) reset sets this bit so that the loop can stabi lize as the mcu is powering up. 1 = pll on 0 = pll off bcs ? base clock select bit this read/write bit sele cts either the crystal oscillator clock (cgmxclk) or t he vco clocks (cgmpclk and cgmvclk) to use as base clocks for the mcu. bcs cannot be set while the pllon bit is clear . after toggling bcs, it may take up to three cgmxcl k and three cgmpclk cycles to complete the transition from one sour ce clock to the other. during the transition, cgmout is held in stasis. (see 8.4.8 base clock selector circuit .) reset clear s the bcs bit. 1 = selects the vco clo cks for the base clock. cgmpclk divided by tw o drives cgmout, cgmvclk (48mhz) drives usbclk 0 = selects the crystal oscill ator clock for the base clock. cgmxclk divided by tw o drives cgmout, cgmxclk drives usbclk note: pllon and bcs have built-in protec tion that prevents the base clock selector circuit from se lecting the vco clock as the source of the base clock if the pll is of f. therefore, pllon cannot be cleared when bcs is set, and bcs cannot be set when pllon is clear. if the pll is off (pllon = 0), selecting cgmpclk/cgmv clk requires two writes to the pll control register. (see 8.4.8 base clock selector circuit .) pre1 and pre0 ? pre scaler program bits these read/write bits control a pre scaler that selects the prescaler power-of-two mult iplier p. (see 8.4.3 pll circuits and 8.4.6 programming the pll .) pre1:pre0 cannot be written when the pllon bit is set. reset clears these bits. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) data sheet mc68HC08KH12a ? rev. 1.0 100 clock generator module (cgm) motorola 8.6.2 pll bandwidth control register (pbwc) the pll bandwidth control register: indicates when the pll is locked in automatic bandwidth control mode , indicates when the pll is in acquisition or tracking mode auto ? automatic bandwidth control bit this read/write bit sele cts automatic or manual bandwidth control. since this cgm is optimized a fr equency output of 48mhz for the usb module, automatic control should be set. reset clears the auto bit. 1 = automatic bandwidth control (recommended) 0 = manual bandwidth control lock ? lock indicator bit when the auto bit is set, lock is a read-only bit that becomes set when the vco clock, cgmvclk, is lo cked (running at the programmed frequency). when the auto bit is clear, lock reads as table 8-3. pre[1:0] programming pre1 pre0 p prescaler multiplier 000 1 011 2 102 4 113 8 address: $003b bit 7654321bit 0 read: auto lock acq 00000 write: reset:00000000 = unimplemented figure 8-4. pll bandwidth control register (pbwc) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) cgm registers mc68HC08KH12a ? rev. 1.0 data sheet motorola clock generator module (cgm) 101 logic zero and has no m eaning. the write one func tion of this bit is reserved for test, so this bit must always be written a zero. reset clears the lock bit. 1 = vco frequency correct or locked 0 = vco frequency inco rrect or unlocked acq ? acquisition mode bit when the auto bit is set, acq is a read-only bit that indicates whether the pll is in acquisition mode or tr acking mode. when the auto bit is clear, acq is a read/write bit that controls whether the pll is in acquisiti on or tracking mode. in automatic bandwidth control mode (auto = 1), the last-written value from manual operati on is stored in a te mporary location and is recovered when manual oper ation resumes. rese t clears this bit, enabling acquisition mode. 1 = tracking mode 0 = acquisition mode 8.6.3 pll multiplier sel ect registers (pmsh:pmsl) the pll multiplier select registers contain the program ming information for the modulo feedback divider. address: $003c pmsh bit 7654321bit 0 read: 0000 mul11 mul10 mul9 mul8 write: reset:00000000 address: $003d pmsl read: mul7 mul6 mul5 mul4 mul3 mul2 mul1 mul0 write: reset:00000010 = unimplemented figure 8-5. pll multiplier se lect registers (pmsh:pmsl) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) data sheet mc68HC08KH12a ? rev. 1.0 102 clock generator module (cgm) motorola mul[11:0] ? multiplier select bits these read/write bits control the m odulo feedback divider that selects the vco frequency mu ltiplier n. (see 8.4.3 pll circuits and 8.4.6 programming the pll .) mul[11:0] cannot be written when the pllon bit in the pctl is set. a value of $0000 in the multiplier select registers configures t he modulo feedback divider the same as a value of $0001. reset initializ es the registers to $002 for a default multiply value of 2. note: the multiplier select bits have built-in pr otection such that they cannot be written when the pll is on (pllon = 1). 8.6.4 pll reference divide r select regi ster (prds) the pll reference divider select r egister contains the programming information for the m odulo reference divider. rds[3:0] ? reference divider select bits these read/write bits control the modul o reference divider that selects the reference division factor r. (see 8.4.3 pll circuits and 8.4.6 programming the pll .) rds[7:0] cannot be written when the pllon bit in the pctl is set. a va lue of $00 in the reference divider select register configur es the reference divider the same as a value of $01. (see 8.4.7 special progr amming exceptions .) reset initializes the register to $01 for a default divide value of 1. note: the reference divider select bits have built-in protection such that they cannot be written when the pll is on (pllon = 1). address: $003f bit 7654321bit 0 read: 0000 rds3 rds2 rds1 rds0 write: reset:00000001 = unimplemented figure 8-6. pll reference divi der select r egister (prds) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) interrupts mc68HC08KH12a ? rev. 1.0 data sheet motorola clock generator module (cgm) 103 8.7 interrupts when the auto bit is set in the pll bandwidth control register (pbwc), the pll can generate a cpu interrupt request ev ery time the lock bit changes state. the pllie bit in the pll control register (pctl) enables cpu interrupts from the pll. pllf, the interrupt flag in the pctl, becomes set whether interrupts ar e enabled or not. when the auto bit is clear, cpu interrupts from the p ll are disabled and pllf reads as logic zero. software should read the lock bit after a pll interrupt request to see if the request was due to an entry into lock or an exit fr om lock. when the pll enters lock, the vco clock, cgmpclk, divided by two can be selected as the cgmout source by setting bcs in the pctl. when the pll exits lock, the vco clock fr equency is corrupt, and appropriate precautions should be taken. if the a pplication is not fr equency sensitive, interrupts should be disabled to prev ent pll interrupt service routines from impeding software performance or from exceeding stack limitations. note: software can select the cgmpclk divided by two as the cgmout source even if the p ll is not locked (lock = 0). therefore, software should make sure the pll is lo cked before setting the bcs bit. 8.8 special modes the wait instruction puts the mcu in low-power-consumption standby modes. 8.8.1 wait mode the wait instruction does not affect the cgm. before entering wait mode, software can disengage and turn off the pll by clearing the bcs and pllon bits in the pll control r egister (pctl) to save power. less power-sensitive applications can dise ngage the pll wit hout turning it off, so that the pll cl ock is immediately availa ble at wait exit. this would also be the case when the p ll is to wake the mcu from wait mode, such as when the pll is fi rst enabled and waitin g for lock, or lock is lost. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) data sheet mc68HC08KH12a ? rev. 1.0 104 clock generator module (cgm) motorola 8.8.2 cgm during break interrupts the system integration module (sim) c ontrols whether status bits in other modules can be cleared during th e break state. the bcfe bit in the sim break flag contro l register (sbfcr) enabl es software to clear status bits during t he break state. (see 7.8.3 break flag control register (bfcr) .) to allow software to clear status bi ts during a break interrupt, write a logic one to the bcfe bit. if a status bit is cleared during the break state, it remains cleared when the mcu exits the break state. to protect the pllf bit dur ing the break state, writ e a logic zero to the bcfe bit. with bcfe at logic zero (its default state), software can read and write the pll control register during the brea k state without affecting the pllf bit. 8.9 acquisition/lock time specifications the acquisition and lo ck times of the pll are, in many applications, the most critical pll desi gn parameters. proper desig n and use of the pll ensures the highest stability and lowest acquisi tion/lock times. 8.9.1 acquisition/lock time definitions typical control systems refer to the ac quisition time or lock time as the reaction time, within specified tolera nces, of the system to a step input. in a pll, the step input occurs when the pll is turned on or when it suffers a noise hit. the tolerance is usually specified as a percent of the step input or when the ou tput settles to the desi red value plus or minus a percent of the frequen cy change. therefore, t he reaction time is constant in this definit ion, regardless of the si ze of the step input. for example, consider a system with a 5 percent acqui sition time tolerance. if a command instruct s the system to change from 0 hz to 1 mhz, the acquisition time is the time ta ken for the frequency to reach 1mhz 50 khz. fifty khz = 5% of the 1 m hz step input. if the system is operating at 1 mhz and suffers a ?100 kh z noise hit, the acquisition time is the time taken to return from 900 khz to 1 mhz 5khz. five khz = 5 percent of the 100-khz step input. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) acquisition/lock time specifications mc68HC08KH12a ? rev. 1.0 data sheet motorola clock generator module (cgm) 105 other systems refer to ac quisition and lock times as the time the system takes to reduce the error between the actual output and the desired output to within specified toleranc es. therefore, the acquisition or lock time varies according to the original error in the output . minor errors may not even be registered. typical pll applications prefer to use this definition because the system requires the out put frequency to be within a certain tolerance of the desired fr equency regardless of the size of the initial error. the discrepancy in these definitions ma kes it difficult to specify an acquisition or lock time for a typical pll. therefor e, the definitions for acquisition and lock times for this module are: acquisition time, t acq , is the time the pll takes to reduce the error between the actual output fr equency and the desired output frequency to less than the tra cking mode entry tolerance, ? trk . acquisition time is based on an initial frequency error, (f des ? f orig )/f des , of not more than 100 percent. in automatic bandwidth control mode (see 8.4.5 manual and automatic pll bandwidth modes .), acquisition time expires when the acq bit becomes set in the pll bandwid th control regi ster (pbwc). lock time, t lock , is the time t he pll takes to reduce the error between the actual output fr equency and the desired output frequency to less than the lo ck mode entry tolerance, ? lock . lock time is based on an in itial frequency error, (f des ? f orig )/f des , of not more than 100 percent. in au tomatic bandwidth control mode, lock time expires when the lock bit becomes se t in the pll bandwidth control regi ster (pbwc). (see 8.4.5 manual and automatic pll bandwidth modes .) obviously, the acquisition and lock ti mes can vary according to how large the frequency error is and may be shorter or longer in many cases. 8.9.2 parametric in fluences on reaction time acquisition and lock times are designed to be as short as possible while still providing the highest possible stability. these reaction times are not constant, however. many factors di rectly and indirect ly affect the acquisition time. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) data sheet mc68HC08KH12a ? rev. 1.0 106 clock generator module (cgm) motorola the most critical parameter which af fects the reaction times of the pll is the reference frequency, f rdv . this frequency is the input to the phase detector and controls how often the pll makes corr ections. for stability, the corrections must be small compared to t he desired frequency, so several corrections are requir ed to reduce the frequency error. therefore, the slower the reference the longer it takes to make these corrections. this parameter is under user control via the choice of crystal frequency f xclk and the r value programmed in the reference divider. (see 8.4.3 pll circuits , 8.4.6 programming the pll , and 8.6.4 pll reference divider sele ct register (prds) .) another critical parameter is the external filter capacitor. the pll modifies the voltage on the vco by adding or subtracting charge from this capacitor. therefore, the rate at which t he voltage changes for a given frequency error (thus change in charge) is propo rtional to the capacitor size. the si ze of the capa citor also is related to the stability of the pll. if the capacitor is too small, the pl l cannot make small enough adjustments to the volt age and the system cannot lo ck. if the capacitor is too large, the pl l may not be able to ad just the voltage in a reasonable time. (see 8.9.3 choosing a filter capacitor .) also important is th e operating voltage po tential applied to v dda . the power supply potential alters the charac teristics of the p ll. a fixed value is best. variable supplies, such as bat teries, are acceptable if they vary within a known range at very slow speeds. noise on the power supply is not acceptable, because it caus es small frequency errors which continually change the acquisi tion time of the pll. temperature and processing also can af fect acquisition time because the electrical characteristics of the pll change. the part operates as specified as long as these influences stay within the specified limits. external factors, however, can caus e drastic changes in the operation of the pll. these factors include noise injected into t he pll through the filter capacitor, filter capacitor leakage, stray impedanc es on the circuit board, and even hum idity or circuit board contamination. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) acquisition/lock time specifications mc68HC08KH12a ? rev. 1.0 data sheet motorola clock generator module (cgm) 107 8.9.3 choosing a filter capacitor as described in 8.9.2 parametric in fluences on re action time , the external filter capacitor, c f , is critical to the stabi lity and reaction time of the pll. the pll is also dependent on reference frequency and supply voltage. the value of t he capacitor must, ther efore, be chosen with supply potential and reference fre quency in mind. for proper operation, the external filter capac itor must be chosen a ccording to this equation: for the value of v dda , choose the voltage potential at which the mcu is operating. if the power supply is va riable, choose a va lue near the middle of the range of possi ble supply values. this equation does not always yield a commonl y available capacitor size, so round to t he nearest available size. if the value is between two different sizes, choose the higher va lue for better stability. choosing the lower size may seem attractive for acquisition time impr ovement, but the pll may become unstable. also, alwa ys choose a capacitor with a tight tolerance ( 20 percent or better ) and low dissipation. 8.9.4 reaction ti me calculation the actual acquisition and lock time s can be calculated using the equations below. these equations yield nominal values under the following conditions: correct selection of filter capacitor, c f (see 8.9.3 choosing a filter capacitor .) room temperature operation negligible external leakage on cgmxfc negligible noise the k factor in the equatio ns is derived from in ternal pll parameters. k acq is the k factor when the pll is configured in acquisition mode, and k trk is the k factor when the pll is configured in tracking mode. (see 8.4.4 acquisition and tracking modes .) reaction time is based on an initial frequency error, (f des ? f orig )/f des , of not more than 100 percent. c f c fact v dda f rdv ------------ - ?? ?? = f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . clock generator module (cgm) data sheet mc68HC08KH12a ? rev. 1.0 108 clock generator module (cgm) motorola note: the inverse proportionality between the lock time a nd the reference frequency. in automatic bandwidth control m ode, the acquisition and lock times are quantized into units based on th e reference frequency. (see 8.4.5 manual and automatic pll bandwidth modes .) a certain number of clock cycles, n acq , is required to ascertain t hat the pll is within the tracking mode entry tolerance, ? trk , before exiting acquisition mode. a certain number of clock cycles, n trk , is required to asce rtain that the pll is within the lock m ode entry tolerance, ? lock . therefore, the acquisition time, t acq , is an integer multiple of n acq /f rdv , and the acquisi tion to lock time, t al , is an integer multiple of n trk /f rdv . in manual mode, it is us ually necessary to wait considerably longer than t lockmax before selecting the pll clock (see 8.4.8 base clock selector circuit .), because the fa ctors described in 8.9.2 parametric influences on reaction time may slow the lock time considerably. automatic bandwidth mode is reco mmended for most users. t acq v dda f rdv ------------ - ?? ?? 8 k acq ------------ - ?? ?? = t al v dda f rdv ------------ - ?? ?? 4 k trk ------------ ?? ?? = t lockmax t acq t al 256t vrdv ++ = f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC08KH12a ? rev. 1.0 data sheet motorola universal serial bus module (usb) 109 data sheet ? mc68HC08KH12a section 9. universal serial bus module (usb) 9.1 contents 9.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 9.3 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 9.4 i/o register description of the hub function . . . . . . . . . . . . . 112 9.4.1 usb hub root port control r egister (hrpcr) . . . . . . . . 116 9.4.2 usb hub downstream port control register (hdp1cr-hdp4cr) . . . . . . . . . . . . . . . . . . . . . . . . . . .117 9.4.3 usb sie timing interr upt register (sietir) . . . . . . . . . . . 119 9.4.4 usb sie timing stat us register (sietsr) . . . . . . . . . . . . 121 9.4.5 usb hub address r egister (haddr). . . . . . . . . . . . . . . . 123 9.4.6 usb hub interrupt register 0 (hir 0) . . . . . . . . . . . . . . . . 124 9.4.7 usb hub control regi ster 0 (hcr0) . . . . . . . . . . . . . . . . 125 9.4.8 usb hub endpoint1 control & data regi ster (hcdr) . . . 127 9.4.9 usb hub status regist er (hsr). . . . . . . . . . . . . . . . . . . .128 9.4.10 usb hub endpoint 0 data registers 0-7 (he0d0-he0d7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130 9.5 i/o register description of the embedded device function . 130 9.5.1 usb embedded devi ce address register (daddr). . . . . 134 9.5.2 usb embedded device interrupt register 0 (dir0) . . . . . 134 9.5.3 usb embedded device interrupt register 1 (dir1) . . . . . 136 9.5.4 usb embedded device control register 0 (dcr0) . . . . . 137 9.5.5 usb embedded device control register 1 (dcr1) . . . . . 139 9.5.6 usb embedded device status register (dsr ) . . . . . . . . . 140 9.5.7 usb embedded device control register 2 (dcr2) . . . . . 142 9.5.8 usb embedded device e ndpoint 0 data registers (de0d0-de0d7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143 9.5.9 usb embedded device e ndpoint 1/2 data registers (de1d0-de1d7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) data sheet mc68HC08KH12a ? rev. 1.0 110 universal serial bus module (usb) motorola 9.2 features features of the gene ral usb module include the following: integrated 3.3 volt regulator with 3.3v output pin regout integrated usb transceiver supp orting both full speed and low speed functions usb data control logic ? packet decoding/generation ? crc generation and checking ? nrzi encoding/decoding ? bit stuffing/de-stuffing usb reset support suspend and resume operations ? remote wakeup support stall, nak, and a ck handshake generation features of the hub functi on include the following: hub control endpoint 0 ? 8-byte transmit buffer ? 8-byte receive buffer hub interrupt endpoint 1 ? 1-byte transmit buffer usb interrupts ? transaction interrupt driven ? start of frame interrupt ? eof2 interrupt ? end of packet interrupt ? signal transition interrupt ? frame timer locked interrupt hub repeater and co ntroller function ? downstream and ups tream connectivity ? bus state evaluation ? selective reset, suspend and resume ? fault condition hardware detection f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) overview mc68HC08KH12a ? rev. 1.0 data sheet motorola universal serial bus module (usb) 111 features of the embedded device f unction include the following: device control endpoint 0 a nd interrupt endpoints 1 and 2 ? 8-byte transmit buffer ? 8-byte receive buffer device interrupt endpoints 1 and 2 ? 8-byte transmit buffer usb generated interrupts ? transaction interrupt driven 9.3 overview this section provides an overview of the universal serial bus (usb) module developed for the mc68hc 08kh12a. this usb module is designed to serve as a compound devi ce, and operates from a reference frequency of 48mhz, derived from the cgm (see section 8. clock generator module (cgm) ). an embedded full speed device function is combined with a hub in a single usb module. fo r the hub sub-module, five basic properties can be support ed by the hardware or the software: connectivity behavior, power managem ent, device connect/disconnect detection, bus fault detection and re covery, and full/low speed device traffic control. endpoi nt 0 of the hub sub -module functions as a receive/transmit control endpoint. endpoint 1 of t he hub sub-module functions as interrupt transfer to r eport the device change state. for the embedded device sub-module, three ty pes of usb data transfers are supported: control, interrupt, and bulk (transmit only). endpoint 0 of the embedded device sub-module functions as a receive/transmit control endpoint. endpoints 1 and 2 of the embedded device sub-module can function as interrupt or bulk, but only in the transmit direction. a block diagram of the usb module is shown figure 9-1 . the usb module manages communications be tween the host and the usb function. the module is par titioned into eight func tional blocks. these blocks consist of a 3.3 volt regulator , a dual function transceiver, the hub repeater function, the si e (serial interface engine), the frame counter logic, the hub control logic, the em bedded device contro l logic, and the endpoint registers. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) data sheet mc68HC08KH12a ? rev. 1.0 112 universal serial bus module (usb) motorola figure 9-1. usb block diagram 9.4 i/o register description of the hub function the usb hub function prov ides a set of contro l/status registers and sixteen data registers that provide storage for t he buffering of data between the usb hub function and the cpu. these regist ers are shown in table 9-1 and table 9-2 . d0+ d0? transceiver 3.3v out cpu bus transceiver d1+ : d4+ d1? : d4? roor port downstream ports hub repeater regulator serial frame counter engine hub control logic registers endpoint 0 - 8/8 b (control) endpoint 1 - 1 b (interrupt) endpoint 0 - 8/8 (control) endpoint 1/2 - 8 b (transmit only, interrupt/bulk) 12mhz usbclk (from cgm) embedded device control logic interface 48mhz f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) i/o register description of the hub function mc68HC08KH12a ? rev. 1.0 data sheet motorola universal serial bus module (usb) 113 table 9-1. hub contro l register summary addr. register name bit 7654321bit 0 $0051 usb hub downstream port 1 control register (hdp1cr) read: pen1 lowsp1 rst1 resum1 susp1 0d1+d1? write: reset:000000xx $0052 usb hub downstream port 2 control register (hdp2cr) read: pen2 lowsp2 rst2 resum2 susp2 0d2+d2? write: reset:000000xx $0053 usb hub downstream port 3 control register (hdp3cr) read: pen3 lowsp3 rst3 resum3 susp3 0d3+d3? write: reset:000000xx $0054 usb hub downstream port 4 control register (hdp4cr) read: pen4 lowsp4 rst4 resum4 susp4 0d4+d4? write: reset:000000xx $0055 unimplemented read: write: reset: $0056 usb sie timing interrupt register (sietir) read: soff eof2f eopf tranf sofie eof2ie eopie tranie write: reset:00000000 $0057 usb sie timing status register (sietsr) read: rstf 0 lockf 00000 write: rstfr lockfr soffr eof2fr eopfr tranfr reset:0**0000000 $0058 usb hub address register (haddr) read: usben add6 add5 add4 add3 add2 add1 add0 write: reset:0**0000000 $0059 usb hub interrupt register 0 (hir0) read: txdf rxdf 0 0 txdie rxdie 00 write: txdfr rxdfr reset:00000000 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) data sheet mc68HC08KH12a ? rev. 1.0 114 universal serial bus module (usb) motorola $005a unimplemented read: write: reset: $005b usb hub control register 0 (hcr0) read: tseq stall0 txe rxe tpsiz3 tpsiz2 tpsiz1 tpsiz0 write: reset:00000000 $005c usb hub endpoint 1 control and data register (hcdr) read: stall1 pnew pchg5 pchg4 pchg3 pchg2 pchg1 pchg0 write: reset:00000000 $005d usb hub status register (hsr) read: rseq setup tx1st 0 rpsiz3 rpsiz2 rpsiz1 rpsiz0 write: tx1str reset:xx00xxxx $005e usb hub root port control register (hrpcr) read: 0 0 0 resum0 suspnd 0d0+d0? write: reset:000000xx = unimplemented x = indeterminate 0** = reset by por only f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) i/o register description of the hub function mc68HC08KH12a ? rev. 1.0 data sheet motorola universal serial bus module (usb) 115 table 9-2. hub data register summary addr. register name bit 7654321bit 0 $0030 usb hub endpoint 0 data register 0 (he0d0) read: he0r07 he0r06 he0r05 he0r 04 he0r03 he0r02 he0r01 he0r00 write: he0t07 he0t06 he0t05 he0t 04 he0t03 he0t02 he0t01 he0t00 reset:xxxxxxxx $0031 usb hub endpoint 0 data register 1 (he0d1) read: he0r17 he0r16 he0r15 he0r 14 he0r13 he0r12 he0r11 he0r10 write: he0t17 he0t16 he0t15 he0t 14 he0t13 he0t12 he0t11 he0t10 reset:xxxxxxxx $0032 usb hub endpoint 0 data register 2 (he0d2) read: he0r27 he0r26 he0r25 he0r 24 he0r23 he0r22 he0r21 he0r20 write: he0t27 he0t26 he0t25 he0t 24 he0t23 he0t22 he0t21 he0t20 reset:xxxxxxxx $0033 usb hub endpoint 0 data register 3 (he0d3) read: he0r37 he0r36 he0r35 he0r 34 he0r33 he0r32 he0r31 he0r30 write: he0t37 he0t36 he0t35 he0t 34 he0t33 he0t32 he0t31 he0t30 reset:xxxxxxxx $0034 usb hub endpoint 0 data register 4 (he0d4) read: he0r47 he0r46 he0r45 he0r 44 he0r43 he0r42 he0r41 he0r40 write: he0t47 he0t46 he0t45 he0t 44 he0t43 he0t42 he0t41 he0t40 reset:xxxxxxxx $0035 usb hub endpoint 0 data register 5 (he0d5) read: he0r57 he0r56 he0r55 he0r 54 he0r53 he0r52 he0r51 he0r50 write: he0t57 he0t56 he0t55 he0t 54 he0t53 he0t52 he0t51 he0t50 reset:xxxxxxxx $0036 usb hub endpoint 0 data register 6 (he0d6) read: he0r67 he0r66 he0r65 he0r 64 he0r63 he0r62 he0r61 he0r60 write: he0t67 he0t66 he0t65 he0t 64 he0t63 he0t62 he0t61 he0t60 reset:xxxxxxxx $0037 usb hub endpoint 0 data register 7 (he0d7) read: he0r77 he0r76 he0r75 he0r 74 he0r73 he0r72 he0r71 he0r70 write: he0t77 he0t76 he0t75 he0t 74 he0t73 he0t72 he0t71 he0t70 reset:xxxxxxxx f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) data sheet mc68HC08KH12a ? rev. 1.0 116 universal serial bus module (usb) motorola 9.4.1 usb hub root port control register (hrpcr) resum0 ? force resume to the root port this read/write bit forces a resume signal (? k? state) on to the usb root port data lines to initiate a remote wakeup. software should control the timing of the forced resume to be between 10 ms and 15 ms. reset clears this bit. 1 = force root port da ta lines to ?k? state 0 = default suspnd ? usb sus pend control bit to save power, this read /write bit should be set by the software if at least 3ms constant idle state is detected on usb bus. setting this bit puts the transceiver and regulato r into a power savings mode. this bit also determines the latch sc heme for the data li nes of the root port and the downstream port. when this bit is 1, the current state shown on the data lines wi ll be reflected to the data register (d+/d?) directly. when the bit is 0, the data register s are the latched state sampled at the last eof2 sample point. the hub repeat er?s function is affected by this bit too. the upstream and downstream traffic will be blocked if this bit is set to 1. when the gl obal resume or the downstream remote wakeup signal is found by the suspend hub, software is responsible to propagat e the traffic between the root port and the enabled downstream port by setting the resumx control bit. reset clears this bit. address: $005e bit 7654321bit 0 read: 0 0 0 resum0 suspnd 0d0+d0? write: reset:000000xx = unimplemented x = indeterminate figure 9-2. usb hub root port contro l register (hrpcr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) i/o register description of the hub function mc68HC08KH12a ? rev. 1.0 data sheet motorola universal serial bus module (usb) 117 eof2 is generated by kh12 every mill isecond, if sof is not detected when three or more eof2 has occurred, software can set the suspnd-bit and put kh 12 into suspend mode. d0+/d0? ? root port differential data these read only bits are the differential data shown on the hub root ports. when the bit suspnd is 0, the data is the latched state at the last eof2 sample point. when the bit suspnd is 1, the data reflects the current state on the data line while accessing this register. 9.4.2 usb hub downstream port control register (hdp1cr-hdp4cr) pen1-pen4 ? downstream port enable control bit this read/write bit determines whet her the enabled or disabled state should be assigned to t he downstream port. se tting this bit 1 to enable the port and clear th e bit to disable t he port. in the enabled state a full-speed port propagates al l downstream signaling, a low- speed port propagates downstream lo w-speed packet traffic when preceded by the preamble pid. an enabled port propagates all upstream signaling including full speed and low speed packets. this address: $0051 bit 7654321bit 0 read: pen1 lowsp1 rst1 resum1 susp1 0d1+d1? write: reset:000000xx address: $0054 read: pen4 lowsp4 rst4 resum4 susp4 0d4+d4? write: reset:000000xx = unimplemented x = indeterminate figure 9-3. usb hub downstream port control registers (hdp1cr-hdp4cr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) data sheet mc68HC08KH12a ? rev. 1.0 118 universal serial bus module (usb) motorola bit can be set to 1 by the host reques t only. it can be cleared either by hardware when a fault condition was detected or by software through the host request. re set clears this bit. 1 = downstream port is enabled 0 = downstream po rt is disabled lowsp1-lowsp4 ? full speed / low speed port control bit this read/write bit spec ifies the attached devic e in the downstream port is low speed device or full s peed device. software is responsible to detect the device atta chment and whether a device is full or low speed. reset clears this bit. 1 = downstream po rt is low speed 0 = downstream port is full speed note: after a port is enabled, hub will automatically generate a low speed keep awake signal to t he port every millisecond. rst1-rst4 ? force reset to the downstream port this read/write bit forces a reset signal ( se0 state) onto the usb downstream port data lines . this bit can be se t by the host request setportfeature (port_reset) only. software should control the timing of the forced reset signali ng downstream for at least 10 ms. reset clears this bit. 1 = force downstream port data lines to se0 state 0 = default resum1-resum4 ? force resume to the downstream port this read/write bit forces a resume signal (? k? state) on to the usb downstream port data lines. this bit is set to reflect the resume signal when the software detects the remo te resume signal on the data lines of the selective suspend downstream port. downstream selective resume sequence to a port may also be initiated via the host request clearportfeature (port_suspend). software should control the timing of the forced re sume signaling downstream for at least 20 ms. to indicate the end of the resume, a low speed eop signal will be followed when this control bit changes from 1 to 0. reset clears this bit. 1 = force downstream port data lines to ?k? state 0 = default f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) i/o register description of the hub function mc68HC08KH12a ? rev. 1.0 data sheet motorola universal serial bus module (usb) 119 susp1-susp4 ? downstream po rt selective suspend bit this read/write bit forces the downstream port entering the selective suspend mode. this bit can be set by the host request setportfeature (port_suspend) only. when this bit is se t, the hub prevents propagating any bus activity (except the port reset or port resume request or the global reset signal) downstream , and the port can only reflect upstream bus state changes via the endpoint 1 of the hub. the blocking occurs at the next eof2 poi nt when this bit is set. reset clears this bit. 1 = force downstream port ent ers the selective suspend mode 0 = default d1+/d1? to d4+/d4? ? downs tream port differential data these read only bits are the diff erential data shown on the hub downstream ports. when t he bit suspnd in the r egister hrpcr is 0, the data is the latched state at th e last eof2 sample point. when the bit suspnd is 1, the dat a reflects the current state on the data line while accessing this register. 9.4.3 usb sie timing inte rrupt register (sietir) address: $0056 bit 7654321bit 0 read: soff eof2f eopf tranf sofie eof2ie eopie tranie write: reset:00000000 = unimplemented figure 9-4. usb sie timing interrupt register (sietir) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) data sheet mc68HC08KH12a ? rev. 1.0 120 universal serial bus module (usb) motorola soff ? start of frame detect flag this read only bit is set when a va lid sof pid is detected on the d0+ and d0? lines at the root port. software must clear this flag by writing a logic 1 to soffr bit in the sietsr register . reset clears this bit. writing to soff has no effect. 1 = start of frame pid has been detected 0 = start of frame pi d has not been detected eof2f ? the second e nd of frame point flag this read only bit is set when the inter nal frame timer co unts to the bit time that the hub mu st see upstream traffi c terminated near the end of frame. this bit time is defined as 10 bit times from the next start of frame pid. software mu st clear this flag by writing a logic 1 to eof2fr bit in the sietsr register. reset clears this bit. writing to eof2f has no effect. 1 = frame timer counts to the eof2 point 0 = frame timer does not count to the eof2 point eopf ? end of packet detect flag this read only bit is set when a va lid end-of-packet sequence is detected on the d0 + and d0? lines. software must clear this flag by writing a logic 1 to the eopfr bit in the sietsr regist er. reset clears this bit. writing to eopf has no effect. 1 = end-of-packet seque nce has been detected 0 = end-of-packet seque nce has not been detected tranf ? bus signal tr ansition detect flag this read only bit is set if there is any bus acti vity on the upstream or the downstream data lines . generally speaking, this bit is used to wakeup the suspended hub when there is any bu s activity occurred. software must clear this flag by writ ing a logic 1 to the tranfr bit in the sietsr register. rese t clears this bit. wr iting to tranf has no effect. 1 = signal transition has been detected 0 = signal transition has not been detected f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) i/o register description of the hub function mc68HC08KH12a ? rev. 1.0 data sheet motorola universal serial bus module (usb) 121 sofie ? start of fr ame interrupt enable this read/write bit enabl es the start of fr ame to generate a usb interrupt when the soff bit becomes set. re set clears this bit. 1 = usb interrupt enabled for start of frame 0 = usb interrupt disabl ed for start of frame eof2ie ? the second end of fr ame point interrupt enable this read/write bi t enables the second end of frame to generate a usb interrupt when the eof2f bit becom es set. reset clears this bit. 1 = usb interrupt en abled for the second end of frame point 0 = usb interrupt disabled for the second end of frame point eopie ? end of packet de tect interrupt enable this read/write bit enabl es the usb to generat e a interrupt request when the eopf bit becomes set. reset clears the bit. 1 = usb interrupt enabl ed for end-of-packe t sequence detection 0 = usb interrupt disabled for end-of-packet sequence detection tranie ? bus signal transitio n detect interrupt enable this read/write bi t enables the signal transit ion to generate a usb interrupt when the tran f bit becomes set. re set clears this bit. 1 = usb interrupt enabled for bus signal transition 0 = usb interrupt disabled for bus signal transition 9.4.4 usb sie timing stat us register (sietsr) address: $0057 bit 7654321bit 0 read: rstf 0 lockf 00000 write: rstfr lockfr soffr eof2fr eopfr tranfr reset:0**0000000 = unimplemented 0** = reset by por only figure 9-5. usb sie timing status register (sietsr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) data sheet mc68HC08KH12a ? rev. 1.0 122 universal serial bus module (usb) motorola rstf ? usb reset flag this read only bit is set when a valid reset signal state is detected on the d0+ and d0- lines. this reset detecti on will also generate an internal reset signal to reset th e cpu and other peripherals including the usb module. this bit is cleared by writing a logic 1 to the rstfr bit. note: ** please note rstf bit is only be reset by a por reset. rstfr ? clear reset indicator bit writing a logic 1 to this write only bit will clear the rstf bit if it is set. writing a logic 0 to the rstfr has no effect. reset clears this bit. lockf ? usb fram e timer locked this read only bit is set when the inte rnal frame timer is locked to the host timer. this bit is cl eared by writing a logic 1 to the lockfr bit. reset clears this bit. lockfr ? clear frame timer locked flag writing a logic 1 to this write only bit wi ll clear the lockf bit if it is set. writing a logic 0 to t he lockfr has no effect. reset clears this bit. soffr ? start of frame flag reset writing a logic 1 to this write only bit will clear t he soff bit if it is set. writing a logic 0 to t he soffr has no effect. reset clears this bit. eof2fr ? the second end of frame point flag reset writing a logic 1 to this write only bit will clear t he eof2f bit if it is set. writing a logic 0 to t he eof2fr has no ef fect. reset clears this bit. eopfr ? end of pa cket flag reset writing a logic 1 to this write only bit will clear the eopf bit if it is set. writing a logic 0 to the eopfr ha s no effect. reset clears this bit. tranfr ? bus signal tr ansition flag reset writing a logic 1 to this write only bit wi ll clear the tranf bi t if it is set. writing a logic 0 to t he tranfr has no effect. reset clears this bit. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) i/o register description of the hub function mc68HC08KH12a ? rev. 1.0 data sheet motorola universal serial bus module (usb) 123 9.4.5 usb hub address register (haddr) usben ? usb module enable this read/write bit enabl es and disables t he usb module. when usben is cleared, t he usb module will not respond to any tokens and the external regul ated output regout will be turned off. note: **usben bit can only be cleared by a por reset. 1 = usb func tion enabled 0 = usb function dis abled, usb transceiver is also disabled to save power. add6-add0 ? usb h ub function address these bits specify the address of t he hub function. reset clears these bits. address: $0058 bit 7654321bit 0 read: usben add6 add5 add4 add3 add2 add1 add0 write: reset:0**0000000 0** = reset by por only figure 9-6. usb hub a ddress register (haddr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) data sheet mc68HC08KH12a ? rev. 1.0 124 universal serial bus module (usb) motorola 9.4.6 usb hub interrupt register 0 (hir0) txdf ? hub endpoint 0 data transmit flag this read only bit is set after the data stored in hub endpoint 0 transmit buffers has been sent an d an ack handshake packet from the host is received. once the next set of data is ready in the transmit buffers, software must clear this fl ag by writing a logi c 1 to the txdfr bit. to enable the next data packet transmission, txe must also be set. if txdf bit is no t cleared, a nak handshake will be returned in the next in transaction. reset clears this bit. writi ng to txdf has no effect. 1 = transmit on hub e ndpoint 0 has occurred 0 = transmit on hub endpoi nt 0 has not occurred rxdf ? hub endpoint 0 data receive flag this read only bit is set after the usb hub function has received a data packet and responded with an ack handshake packet. software must clear this flag by wr iting a logic 1 to the r xdfr bit after all of the received data has been read. software must also set rxe bit to one to enable the next data packet recepti on. if rxdf bit is not cleared, a nak handshake will be re turned in the next out transaction. reset clears this bit. writi ng to rxdf has no effect. 1 = receive on hub end point 0 has occurred 0 = receive on hub endpoi nt 0 has not occurred address: $0059 bit 7654321bit 0 read: txdf rxdf 0 0 txdie rxdie 0 0 write: txdfr rxdfr reset:00000000 = unimplemented figure 9-7. usb hub inte rrupt register 0 (hir0) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) i/o register description of the hub function mc68HC08KH12a ? rev. 1.0 data sheet motorola universal serial bus module (usb) 125 txdie ? hub endpoint 0 tr ansmit interrupt enable this read/write bi t enables the transmit h ub endpoint 0 to generate cpu interrupt requests when the txdf bit becomes set. reset clears the txdie bit. 1 = usb interrupt enabled for transmi t hub endpoint 0 0 = usb interrupt disabled for transmit hub endpoint 0 rxdie ? hub endpoint 0 re ceive interrupt enable this read/write bi t enables the receive hub endpoint 0 to generate cpu interrupt requests w hen the rxdf bit becomes set. reset clears the rxdie bit. 1 = usb interrupt enabled for receiv e hub endpoint 0 0 = usb interrupt disabled for receive hub endpoint 0 txdfr ? hub endpoint 0 transmit flag reset writing a logic 1 to this wr ite only bit will cl ear the txdf bit if it is set. writing a logic 0 to t xdfr has no effect. reset clears this bit. rxdfr ? hub endpoint 0 receive flag reset writing a logic 1 to this write only bit will clear the rxdf bit if it is set. writing a logic 0 to rxdfr has no effect. reset clears this bit. 9.4.7 usb hub contro l register 0 (hcr0) address: $005b bit 7654321bit 0 read: tseq stall0 txe rxe tpsiz3 tpsiz2 tpsiz1 tpsiz0 write: reset:00000000 figure 9-8. usb hub cont rol register 0 (hcr0) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) data sheet mc68HC08KH12a ? rev. 1.0 126 universal serial bus module (usb) motorola tseq ? hub endpoint 0 transmit sequence bit this read/write bit deter mines which type of da ta packet (data0 or data1) will be sent during the next in tr ansaction directed at endpoint 0. toggling of this bit must be controlled by software. reset clears this bit. 1 = data1 token active for ne xt hub endpoint 0 transmit 0 = data0 token active for ne xt hub endpoint 0 transmit stall0 ? hub endpoint 0 force stall bit this read/write bit c auses hub endpoint 0 to return a stall handshake when polled by either an in or out token by the host. the usb hardware clears this bit when a setup token is received. reset clears this bit. 1 = send stall handshake 0 = default txe ? hub endpoint 0 transmit enable this read/write bi t enables a transmit to occur when the usb host controller sends an in token to t he hub endpoint 0. software should set this bit when data is ready to be transmitted. it must be cleared by software when no more hub endpoi nt 0 data packets needs to be transmitted. if this bit is 0 or the tx df is set, the usb will respond with a nak handshake to any hu b endpoint 0 in tokens. reset clears this bit. 1 = data is ready to be sent 0 = data is not ready. respond with nak rxe ? hub endpoint 0 receive enable this read/write bi t enables a receive to o ccur when the usb host controller sends an out token to the hub endpoint 0. software should set this bit when data is ready to be received. it must be cleared by software when data cannot be received. if this bit is 0 or the rxdf is set, the usb will respond with a nak handshake to any hub endpoint 0 out tokens. reset clears this bit. 1 = data is ready to be received 0 = not ready for data. respond with nak f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) i/o register description of the hub function mc68HC08KH12a ? rev. 1.0 data sheet motorola universal serial bus module (usb) 127 tpsiz3-tpsiz0 ? hub endpoint 0 transmit data packet size these read/write bits st ore the number of trans mit data bytes for the next in token request fo r hub endpoint 0. thes e bits are cleared by reset. 9.4.8 usb hub endpoi nt1 control & data register (hcdr) stall1 ? hub endpoint 1 force stall bit this read/write bit c auses hub endpoint 1 to return a stall handshake when polled by the hos t. reset clears this bit. 1 = send stall handshake 0 = default pnew ? port new status change this read/write bi t enables a transmit to occur when the usb host controller sends an in token to hub endpoint 1. software should set this bit when there is any status change on the downstream ports, embedded device or hub. it must be cleared by software when there is no status change needs to be r eported to the host through the endpoint1. if this bi t is 0, a nak handshake wi ll be returned for next in token for hub endpoint 1. reset clears this bit. 1 = port status change bi t is ready to be sent. 0 = port status does not change. respond with nak. address: $005c bit 7654321bit 0 read: stall1 pnew pchg5 pchg4 pchg3 pchg2 pchg1 pchg0 write: reset:00000000 figure 9-9. usb hub cont rol register 1 (hcr1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) data sheet mc68HC08KH12a ? rev. 1.0 128 universal serial bus module (usb) motorola pchg5-pchg0 ? hub and po rt status change bits these read/write bits report the st atus change for the hub, embedded device and the four downstream por ts. the status change bitmap is returned to the host th rough the hub endpoint 1 if the bit pnew is 1. these bits are cleared by reset. 9.4.9 usb hub status register (hsr) bit name function value description pchg0 hub status change 0 no status change in hub 1 hub status change detected pchg1 port 1 status change 0 no status change in port 1 1 port 1 status change detected pchg2 port 2 status change 0 no status change in port 2 1 port 2 status change detected pchg3 port 3 status change 0 no status change in port 3 1 port 3 status change detected pchg4 port 4 status change 0 no status change in port 4 1 port 4 status change detected pchg5 embedded device status change 0 no status change in embedded device 1 embedded device status change detected address: $005d bit 7654321bit 0 read: rseq setup tx1st 0 rpsiz3 rpsiz2 rpsiz1 rpsiz0 write: tx1str reset:xx00xxxx figure 9-10. u sb hub status r egister (hsr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) i/o register description of the hub function mc68HC08KH12a ? rev. 1.0 data sheet motorola universal serial bus module (usb) 129 rseq ? hub endpoint 0 receive sequence bit this read only bit indica tes the type of data packet last received for hub endpoint 0 (dat a0 or data1). 1 = data1 token received in la st hub endpoint 0 receive 0 = data0 token received in la st hub endpoint 0 receive setup ? hub setup token detect bit this read only bit indi cates that a valid setup token has been received. 1 = last token rece ived for hub endpoint 0 was a setup token 0 = last token received for hub endpoi nt 0 was not a setup token tx1st ? hub transmit first flag this read only bit is set if the hub endpoint 0 da ta transmit flag (txdf) is set when the u sb control logic is se tting the hub endpoint 0 data receive flag (rxdf). in other words, if an unserviced endpoint 0 transmit flag is stil l set at the end of an endpoint 0 reception, then this bit w ill be set. this bit lets the firmware know that the endpoint 0 tr ansmission happened befor e the endpoint 0 reception. reset clears this bit. 1 = in transaction occu rred before setup/out 0 = in transaction occu rred after setup/out tx1str ? clear hub transmit first flag writing a logic 1 to this wr ite only bit will clear the tx1st bit if it is set. writing a logic 0 to t he tx1str has no effect. reset clears this bit. rpsiz3-rpsiz0 ? hub endpoint 0 receive data packet size these read only bits store the number of data by tes received for the last out or setup transaction fo r hub endpoint 0. these bits are not affected by reset. = unimplemented x = indeterminate figure 9-10. u sb hub status r egister (hsr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) data sheet mc68HC08KH12a ? rev. 1.0 130 universal serial bus module (usb) motorola 9.4.10 usb hub endp oint 0 data register s 0-7 (he0d0-he0d7) he0rx7-he0rx0 ? hub endpoint 0 receive data buffer these read only bits are serially loaded with out token or setup token data directed at hub endpoint 0. the data is received over the usb?s d0+ and d0? pins. he0tx7-he0tx0 ? hub endpoint 0 transmit data buffer these write only buffers are loaded by software with data to be sent on the usb bus on the next in to ken directed at hub endpoint 0. 9.5 i/o register description of the embedded device function the usb embedded device func tion provides a set of control/status registers and twenty-four data registers that provide storage for the buffering of data between the usb embedded device function and the cpu. these register s are shown in table 9-3 and table 9-4 . address: $0030 bit 7654321bit 0 read: he0r07 he0r06 he0r05 he0r04 he0r03 he0r02 he0r01 he0r00 write: he0t07 he0t06 he0t05 he0t 04 he0t03 he0t02 he0t01 he0t00 reset:xxxxxxxx address: $0037 read: he0r77 he0r76 he0r75 he0r74 he0r73 he0r72 he0r71 he0r70 write: he0t77 he0t76 he0t75 he0t 74 he0t73 he0t72 he0t71 he0t70 reset:xxxxxxxx x = indeterminate figure 9-11. u sb hub endpoint 0 data r egister (he0d0-he0d7) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) i/o register description of the embedded device function mc68HC08KH12a ? rev. 1.0 data sheet motorola universal serial bus module (usb) 131 table 9-3. embedded device control register summary addr. register name bit 7654321bit 0 $0047 usb embedded device control register 2 (dcr2) read: 0000 enable2 enable1 dstall2 dstall1 write: reset:00000000 $0048 usb embedded device address register (daddr) read: deven dadd6 dadd5 dadd4 dadd3 dadd2 dadd1 dadd0 write: reset:00000000 $0049 usb embedded device interrupt register 0 (dir0) read: txd0f rxd0f 0 0 txd0ie rxd0ie 00 write: txd0fr rxd0fr reset:00000000 $004a usb embedded device interrupt register 1 (dir1) read: txd1f 0 0 0 txd1ie 000 write: txd1fr reset:00000000 $004b usb embedded device control register 0 (dcr0) read: t0seq dstall0 tx0e rx0e tp0siz3 tp0siz2 tp0siz1 tp0siz0 write: reset:00000000 $004c usb embedded device control register 1 (dcr1) read: t1seq endadd tx1e 0 tp1siz3 tp1siz2 tp1siz1 tp1siz0 write: reset:00000000 $004d usb embedded device status register (dsr) read: drseq dsetup dtx1st 0 rp0siz3 rp0siz2 rp0siz1 rp0siz0 write: dtx1str reset:xx00xxxx = unimplemented x = indeterminate f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) data sheet mc68HC08KH12a ? rev. 1.0 132 universal serial bus module (usb) motorola table 9-4. embedded device data register summary addr. register name bit 7654321bit 0 $0020 usb embedded device endpoint 0 data register 0 (de0d0) read: de0r07 de0r06 de0r05 de0r 04 de0r03 de0r02 de0r01 de0r00 write: de0t07 de0t06 de0t05 de0t 04 de0t03 de0t02 de0t01 de0t00 reset:xxxxxxxx $0021 usb embedded device endpoint 0 data register 1 (de0d1) read: de0r17 de0r16 de0r15 de0r 14 de0r13 de0r12 de0r11 de0r10 write: de0t17 de0t16 de0t15 de0t 14 de0t13 de0t12 de0t11 de0t10 reset:xxxxxxxx $0022 usb embedded device endpoint 0 data register 2 (de0d2) read: de0r27 de0r26 de0r25 de0r 24 de0r23 de0r22 de0r21 de0r20 write: de0t27 de0t26 de0t25 de0t 24 de0t23 de0t22 de0t21 de0t20 reset:xxxxxxxx $0023 usb embedded device endpoint 0 data register 3 (de0d3) read: de0r37 de0r36 de0r35 de0r 34 de0r33 de0r32 de0r31 de0r30 write: de0t37 de0t36 de0t35 de0t 34 de0t33 de0t32 de0t31 de0t30 reset:xxxxxxxx $0024 usb embedded device endpoint 0 data register 4 (de0d4) read: de0r47 de0r46 de0r45 de0r 44 de0r43 de0r42 de0r41 de0r40 write: de0t47 de0t46 de0t45 de0t 44 de0t43 de0t42 de0t41 de0t40 reset:xxxxxxxx $0025 usb embedded device endpoint 0 data register 5 (de0d5) read: de0r57 de0r56 de0r55 de0r 54 de0r53 de0r52 de0r51 de0r50 write: de0t57 de0t56 de0t55 de0t 54 de0t53 de0t52 de0t51 de0t50 reset:xxxxxxxx $0026 usb embedded device endpoint 0 data register 6 (de0d6) read: de0r67 de0r66 de0r65 de0r 64 de0r63 de0r62 de0r61 de0r60 write: de0t67 de0t66 de0t65 de0t 64 de0t63 de0t62 de0t61 de0t60 reset:xxxxxxxx $0027 usb embedded device endpoint 0 data register 7 (de0d7) read: de0r77 de0r76 de0r75 de0r 74 de0r73 de0r72 de0r71 de0r70 write: de0t77 de0t76 de0t75 de0t 74 de0t73 de0t72 de0t71 de0t70 reset:xxxxxxxx f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) i/o register description of the embedded device function mc68HC08KH12a ? rev. 1.0 data sheet motorola universal serial bus module (usb) 133 $0028 usb embedded device endpoint 1/2 data register 0 (de1d0) read: write: de1t07 de1t06 de1t05 de1t 04 de1t03 de1t02 de1t01 de1t00 reset:xxxxxxxx $0029 usb embedded device endpoint 1/2 data register 1 (de1d1) read: write: de1t17 de1t16 de1t15 de1t 14 de1t13 de1t12 de1t11 de1t10 reset:xxxxxxxx $002a usb embedded device endpoint 1/2 data register 2 (de1d2) read: write: de1t27 de1t26 de1t25 de1t 24 de1t23 de1t22 de1t21 de1t20 reset:xxxxxxxx $002b usb embedded device endpoint 1/2 data register 3 (de1d3) read: write: de1t37 de1t36 de1t35 de1t 34 de1t33 de1t32 de1t31 de1t30 reset:xxxxxxxx $002c usb embedded device endpoint 1/2 data register 4 (de1d4) read: write: de1t47 de1t46 de1t45 de1t 44 de1t43 de1t42 de1t41 de1t40 reset:xxxxxxxx $002d usb embedded device endpoint 1/2 data register 5 (de1d5) read: write: de1t57 de1t56 de1t55 de1t 54 de1t53 de1t52 de1t51 de1t50 reset:xxxxxxxx $002e usb embedded device endpoint 1/2 data register 6 (de1d6) read: write: de1t67 de1t66 de1t65 de1t 64 de1t63 de1t62 de1t61 de1t60 reset:xxxxxxxx $002f usb embedded device endpoint 1/2 data register 7 (de1d7) read: write: de1t77 de1t76 de1t75 de1t 74 de1t73 de1t72 de1t71 de1t70 reset:xxxxxxxx f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) data sheet mc68HC08KH12a ? rev. 1.0 134 universal serial bus module (usb) motorola 9.5.1 usb embedded device address register (daddr) deven ? enable u sb embedded device these bit enable or disable the embed ded device function. it is used together with pen1-pen 4 to control the e numeration sequence. reset clears these bits. 1 = usb embedded device enabled 0 = usb embedded de vice disabled dadd6-dadd0 ? usb embedded device function address these bits specify the address of the embedded device function. reset clears these bits. 9.5.2 usb embedded device inte rrupt register 0 (dir0) address: $0048 bit 7654321bit 0 read: deven dadd6 dadd5 dadd4 dadd3 dadd2 dadd1 dadd0 write: reset:00000000 figure 9-12. usb em bedded device address re gister (daddr) address: $0049 bit 7654321bit 0 read: txd0f rxd0f 0 0 txd0ie rxd0ie 0 0 write: txd0fr rxd0fr reset:00000000 = unimplemented figure 9-13. usb em bedded device interrup t register 0 (dir0) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) i/o register description of the embedded device function mc68HC08KH12a ? rev. 1.0 data sheet motorola universal serial bus module (usb) 135 txd0f ? embedded device endpo int 0 data transmit flag this read only bit is set after t he data stored in embedded device endpoint 0 transmit buffers has been sent and an ack handshake packet from the host is received. once the next set of data is ready in the transmit buffers, software must clear this flag by writing a logic 1 to the txd0fr bit. to enable the next data packet transmission, tx0e must also be set. if txd0f bit is not cleared, a nak handshake will be returned in the ne xt in transaction. reset clears this bit. writing to txd0f has no effect. 1 = transmit on embedded devic e endpoint 0 has occurred 0 = transmit on embedded device endpoint 0 has not occurred rxd0f ? embedded device end point 0 data receive flag this read only bit is set after the usb embedded dev ice module has received a data packet and re sponded with an ack handshake packet. software must clear this fl ag by writing a logic 1 to the rxd0fr bit after all of the rece ived data has been read. software must also set rx0e bit to one to enable the next data packet reception. if rxd0f bit is no t cleared, a nak handshake will be returned in the next out transaction. reset clears this bit. writi ng to rxd0f has no effect. 1 = receive on embedded device endpoint 0 has occurred 0 = receive on embedded device endpoint 0 has not occurred txd0ie ? embedded device endpoint 0 transmit interrupt enable this read/write bit e nables the transmit embedded device endpoint 0 to generate cpu interr upt requests when t he txd0f bit becomes set. reset clears the txd0ie bit. 1 = transmit embedded device endpoint 0 can generate a cpu interrupt request 0 = transmit embedded device endpoint 0 cannot generate a cpu interrupt request rxd0ie ? embedded device endpoin t 0 receive interrupt enable this read/write bit e nables the receive embedded device endpoint 0 to generate cpu interr upt requests when the rxd0f bit becomes set. reset clears the rxd0ie bit. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) data sheet mc68HC08KH12a ? rev. 1.0 136 universal serial bus module (usb) motorola 1 = receive embedded device e ndpoint 0 can generate a cpu interrupt request 0 = receive embedded device e ndpoint 0 cannot generate a cpu interrupt request txd0fr ? embedded device en dpoint 0 transmit flag reset writing a logic 1 to this write only bit will clear the txd0f bi t if it is set. writing a logic 0 to t xd0fr has no effect. reset clears this bit. rxd0fr ? embedded device e ndpoint 0 receive flag reset writing a logic 1 to this write only bit will clear th e rxd0f bit if it is set. writing a logic 0 to rxd0fr has no effect. reset clears this bit. 9.5.3 usb embedded device inte rrupt register 1 (dir1) txd1f ? embedded device endpo int 1/2 data transmit flag this read only bit is shared by e ndpoint 1 and endpoint 2 of the embedded device. it is set after the da ta stored in th e shared endpoint 1/2 transmit buffer of the embedded device has been sent and an ack handshake packet from the host is received. once the next set of data is ready in the transmit buffers, software must clear this flag by writing a logic 1 to the txd1fr bit. to enable the next data packet transmission, tx1e must also be set. if txd1 f bit is not cleared, a nak handshake will be returned in the next in transaction. reset clears this bit. writing to txd1f has no effect. address: $004a bit 7654321bit 0 read: txd1f 0 0 0 txd1ie 0 0 0 write: txd1fr reset:00000000 = unimplemented figure 9-14. usb em bedded device interrup t register 1 (dir1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) i/o register description of the embedded device function mc68HC08KH12a ? rev. 1.0 data sheet motorola universal serial bus module (usb) 137 1 = transmit on endpoint 1 or endpoint 2 of the embedded device has occurred 0 = transmit on endpoint 1 or endpoint 2 of the embedded device has not occurred txd1ie ? embedded device endpoint 1/2 transmi t interrupt enable this read/write bit enabl es the usb to gener ate cpu interrupt requests when the shared transmit e ndpoint 1/2 interr upt flag bit of the embedded device (txd1f) be comes set. reset clears the txd1ie bit. 1 = transmit embedded device en dpoints 1 and 2 can generate a cpu interrupt request 0 = transmit embedded device end points 1 and 2 cannot generate a cpu interrupt request txd1fr ? embedded device endpoi nt 1/2 transmit flag reset writing a logic 1 to this write only bit will clear the txd1f bi t if it is set. writing a logic 0 to t xd1fr has no effect. reset clears this bit. 9.5.4 usb embedded device c ontrol register 0 (dcr0) t0seq ? embedded device endpoi nt 0 transmit sequence bit this read/write bit deter mines which type of da ta packet (data0 or data1) will be sent during the next in tr ansaction directed at endpoint 0. toggling of this bit must be controlled by software. reset clears this bit. address: $004b bit 7654321bit 0 read: t0seq dstall0 tx0e rx0e tp0siz3 tp0siz2 tp0siz1 tp0siz0 write: reset:00000000 figure 9-15. usb em bedded device control register 0 (dcr0) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) data sheet mc68HC08KH12a ? rev. 1.0 138 universal serial bus module (usb) motorola 1 = data1 token active for ne xt embedded device endpoint 0 transmit 0 = data0 token active for ne xt embedded device endpoint 0 transmit dstall0 ? embedded de vice endpoint 0 force stall bit this read/write bit caus es embedded device endpoint 0 to return a stall handshake when polle d by either an in or out token by the host. the usb hardware clears th is bit when a setup token is received. reset clears this bit. 1 = send stall handshake 0 = default tx0e ? embedded device e ndpoint 0 transmit enable this read/write bi t enables a transmit to occur when the usb host controller sends an in token to the embedded devic e endpoint 0. software should set this bit when dat a is ready to be transmitted. it must be cleared by software when no more embedded device endpoint 0 data needs to be transmitted. if this bit is 0 or the txd0f is set, the usb will re spond with a nak handshake to any embedded device e ndpoint 0 in tokens. reset clears this bit. 1 = data is ready to be sent 0 = data is not ready. respond with nak rx0e ? embedded device e ndpoint 0 re ceive enable this read/write bi t enables a receive to o ccur when the usb host controller sends an out token to the embedded device endpoint 0. software should set this bit when data is ready to be received. it must be cleared by software w hen data cannot be received. if this bit is 0 or the rxd0f is set, the usb wil l respond with a nak handshake to any embedded device e ndpoint 0 out tokens. reset clears this bit. 1 = data is ready to be received 0 = not ready for data. respond with nak f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) i/o register description of the embedded device function mc68HC08KH12a ? rev. 1.0 data sheet motorola universal serial bus module (usb) 139 tp0siz3-tp0siz0 ? em bedded device endpoint 0 transmit data packet size these read/write bits st ore the number of trans mit data bytes for the next in token request for embedded device endpoint 0. these bits are cleared by reset. 9.5.5 usb embedded device c ontrol register 1 (dcr1) t1seq ? embedded device endpoi nt 1/2 transmit sequence bit this read/write bit deter mines which type of da ta packet (data0 or data1) will be sent during the next in tr ansaction directed to embedded device endpoint 1 or 2. tog gling of this bit must be controlled by software. reset clears this bit. 1 = data1 token active for ne xt embedded device endpoint 1/2 transmit 0 = data0 token active for ne xt embedded device endpoint 1/2 transmit endadd ? endpoint address select this read/write bit spec ifies whether the data inside the registers de1d0-de1d7 are used for embedded dev ice endpoint 1 or 2. if all the conditions for a successful endpoint 2 usb response to a host?s in token are satisfied (txd1 f=0, tx1e=1, dstall2=0, and enable2=1) except that the endadd bit is configured for endpoint 1, the usb responds wit h a nak handshake packet. reset clears this bit. address: $004c bit 7654321bit 0 read: t1seq endadd tx1e 0 tp1siz3 tp1siz2 tp1siz1 tp1siz0 write: reset:00000000 = unimplemented figure 9-16. usb em bedded device control register 1 (dcr1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) data sheet mc68HC08KH12a ? rev. 1.0 140 universal serial bus module (usb) motorola 1 = the data buffers are used fo r embedded device endpoint 2 0 = the data buffers are used fo r embedded device endpoint 1 tx1e ? embedded device endpo int 1/2 transmit enable this read/write bi t enables a transmit to occur when the usb host controller sends an in token to endpoint 1 or en dpoint 2 of the embedded device. the appropria te endpoint enable bit, enable1 or enable2 bit in the dcr 2 register, should al so be set. software should set the tx1e bit when data is ready to be transmitted. it must be cleared by software when no more data nee ds to be transmitted. if this bit is 0 or the txd1f is set, the usb will re spond with a nak handshake to any endpoint 1 or endpoi nt 2 directed in tokens. reset clears this bit. 1 = data is ready to be sent. 0 = data is not ready. respond with nak. tp1siz3-tp1siz0 ? em bedded device endpoint 1/2 transmit data packet size these read/write bits st ore the number of trans mit data bytes for the next in token request for embedded dev ice endpoint 1 or endpoint 2. these bits are cleared by reset. 9.5.6 usb embedded device status register (dsr) address: $004d bit 7654321bit 0 read: drseq dsetup dtx1st 0 rp0siz3 rps0iz2 rp0siz1 rp0siz0 write: dtx1str reset:xx00xxxx = unimplemented x = indeterminate figure 9-17. usb embedded devi ce status register (dsr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) i/o register description of the embedded device function mc68HC08KH12a ? rev. 1.0 data sheet motorola universal serial bus module (usb) 141 drseq ? embedded devi ce endpoint 0 receive sequence bit this read only bit indica tes the type of data packet last received for embedded device endpoint 0 (data0 or data1). 1 = data1 token received in la st embedded device endpoint 0 receive 0 = data0 token received in la st embedded device endpoint 0 receive dsetup ? embedded device se tup token detect bit this read only bit indi cates that a valid setup token has been received. 1 = last token rece ived for endpoint 0 was a setup token 0 = last token receiv ed for endpoint 0 was not a setup token dtx1st ? embedded device transmit first flag this read only bit is set if the embedded device endpoint 0 data transmit flag (txd0f) is set when the usb contro l logic is setting the embedded device endpoint 0 data rece ive flag (rxd 0f). in other words, if an unserviced endpoint 0 transmit flag is still set at the end of an endpoint 0 reception, then this bit will be set. this bit lets the firmware know that the endpoint 0 transmission happened before the endpoint 0 reception. reset clears this bit. 1 = in transaction occu rred before setup/out 0 = in transaction occu rred after setup/out dtx1str ? clear transmit first flag writing a logic 1 to this write only bit will clear t he dtx1st bit if it is set. writing a logic 0 to the dtx1st r has no effect. reset clears this bit. rp0siz3-rp0siz0 ? embedded devi ce endpoint 0 receive data packet size these read only bits store the number of data by tes received for the last out or setup transaction for embedded device endpoint 0. these bits are not affected by reset. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) data sheet mc68HC08KH12a ? rev. 1.0 142 universal serial bus module (usb) motorola 9.5.7 usb embedded device c ontrol register 2 (dcr2) enable2 ? embedded devi ce endpoint 2 enable this read/write bit enabl es embedded device endp oint 2 and allows the usb to respond to in packets addressed to this endpoint. reset clears this bit. 1 = embedded device e ndpoint 2 is enabled a nd can respond to an in token 0 = embedded device endpoi nt 2 is disabled enable1 ? embedded devi ce endpoint 1 enable this read/write bit enabl es embedded device endp oint 1 and allows the usb to respond to in packets addressed to this endpoint. reset clears this bit. 1 = embedded device e ndpoint 1 is enabled a nd can respond to an in token 0 = embedded device endpoi nt 1 is disabled dstall2 ? embedded de vice endpoint 2 force stall bit this read/write bit caus es embedded device endpoint 2 to return a stall handshake when polle d by either an in or out token by the usb host controller. reset clears this bit. 1 = send stall handshake 0 = default address: $0047 bit 7654321bit 0 read: 0 0 0 0 enable2 enable1 dstall2 dstall1 write: reset:00000000 = unimplemented figure 9-18. usb em bedded device control register 2 (dcr2) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) i/o register description of the embedded device function mc68HC08KH12a ? rev. 1.0 data sheet motorola universal serial bus module (usb) 143 dstall1 ? embedded de vice endpoint 1 force stall bit this read/write bit caus es embedded device endpoint 1 to return a stall handshake when polle d by either an in or out token by the usb host controller. reset clears this bit. 1 = send stall handshake 0 = default 9.5.8 usb embedded device endpoint 0 data registers (de0d0-de0d7) de0rx7-de0rx0 ? embedded device endpoint 0 receive data buffer these read only bits are serially loaded with out token or setup token data directed at embedded dev ice endpoint 0. the data is received over the usb?s d0+ and d0? pins. de0tx7-de0tx0 ? embedded device e ndpoint 0 transmit data buffer these write only buffers are loaded by software with data to be sent on the usb bus on the next in to ken directed at embedded device endpoint 0. address: $0020 bit 7654321bit 0 read: de0r07 de0r06 de0r05 de0r04 de0r03 de0r02 de0r01 de0r00 write: de0t07 de0t06 de0t05 de0t 04 de0t03 de0t02 de0t01 de0t00 reset:xxxxxxxx address: $0027 read: de0r77 de0r76 de0r75 de0r74 de0r73 de0r72 de0r71 de0r70 write: de0t77 de0t76 de0t75 de0t 74 de0t73 de0t72 de0t71 de0t70 reset:xxxxxxxx x = indeterminate figure 9-19. usb em bedded device endpoint 0 data register (ue0d0-ue0d7) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . universal serial bus module (usb) data sheet mc68HC08KH12a ? rev. 1.0 144 universal serial bus module (usb) motorola 9.5.9 usb embedded device endpoint 1/ 2 data registers (de1d0-de1d7) de1td7-de1td0 ? embedded device endpoint 1/ endpoint 2 transmit data buffer these write only buffers are loaded by software with data to be sent on the usb bus on the next in to ken directed at endpoint 1 or endpoint 2 of the embedded device. these buffers are shared by embedded device endpoints 1 a nd 2 and depend on proper configuration of the endadd bit. address: $0028 bit 7654321bit 0 read: write: de1t07 de1t06 de1t05 de1t 04 de1t03 de1t02 de1t01 de1t00 reset:xxxxxxxx address: $002f read: write: de1t77 de1t76 de1t75 de1t 74 de1t73 de1t72 de1t71 de1t70 reset:xxxxxxxx = unimplemented x = indeterminate figure 9-20. usb em bedded device endpoint 0 data register (ue0d0-ue0d7) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC08KH12a ? rev. 1.0 data sheet motorola monitor rom (mon) 145 data sheet ? mc68HC08KH12a section 10. monitor rom (mon) 10.1 contents 10.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 10.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 10.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146 10.4.1 entering monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 10.4.2 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 10.4.3 echoing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 10.4.4 break signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 10.4.5 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 10.4.6 baud rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155 10.2 introduction this section describes the monito r rom. the monitor rom allows complete testing of the mcu through a single-wire interface with a host computer. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) data sheet mc68HC08KH12a ? rev. 1.0 146 monitor rom (mon) motorola 10.3 features features of the monitor rom include the following: normal user-mode pin functionality one pin dedicated to serial communication between monitor rom and host computer standard mark/space non-retu rn-to-zero (nrz ) communication with host computer 4800 baud to 28.8 kbaud communi cation with host computer execution of code in ram or rom 10.4 functional description the monitor rom receives and exec utes commands from a host computer. figure 10-1 shows a sample circuit used to enter monitor mode and communicate with a host computer via a standard rs-232 interface. simple monitor commands can access any memory address. in monitor mode, the mcu can exec ute host-computer code in ram while all mcu pins retain normal operating mode functions. all communication between the host computer and the m cu is through the pta0 pin. a level-shifting and multiplexing in terface is required between pta0 and the host computer. pta0 is used in a wired-or configuration and requires a pull-up resistor. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) functional description mc68HC08KH12a ? rev. 1.0 data sheet motorola monitor rom (mon) 147 figure 10-1. moni tor mode circuit + + + + 10m ? x1 v dd v dd + v hi mc145407 mc74hc125 68hc08 rst irq1 /v pp osc1 osc2 v ss2 v ssa v dd 1 pa0 v dd 10k ? 0.1 f 10 ? 6 5 2 4 3 1 db-25 2 3 7 20 18 17 19 16 15 v dd v dd v dd 20pf 20pf 10 f 10 f 10 f 10 f 1 2 4 7 14 3 0.1 f 4.9152mhz 10 k ? pc3 v dd 10k ? b a notes: position a ? bus clock = cgmxclk 4 position b ? bus clock = cgmxclk 2 (see note.) 5 6 v ss1 pc0 pc1 v dd 10k ? v dda 0.1 f v dd pa7 v dd 2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) data sheet mc68HC08KH12a ? rev. 1.0 148 monitor rom (mon) motorola 10.4.1 entering monitor mode table 10-1 shows the pin conditions for entering monitor mode. if ptc3 is low upon moni tor mode entry, cg mout is equal to the crystal frequency. the bus frequency in this case is a divide-by-two of the input clock. if ptc3 is high upon monito r mode entry, the bus frequency will be a divide-by-four of the input clock. note: holding the ptc3 pin low when ent ering monitor mode causes a bypass of a divide-by-two stage at the oscillator. the cgmout frequency is equal to the cgmxclk frequency, and the osc1 i nput directly generates internal bus clocks. in th is case, the osc1 signal must have a 50% duty cycle at maximum bus frequency. enter monitor mode with the pin co nfiguration shown above by pulling rst low and then high. the rising edge of rst latches monitor mode. once monitor mode is la tched, the values on th e specified pins can change. once out of reset, t he mcu monitor mode firmwa re then sends a break signal (10 consecutive logi c zeros) to the host co mputer, indicating that it is ready to receive a command. the break signal also provides a timing reference to allow t he host to determine t he necessary baud rate. monitor mode uses differ ent vectors for reset, swi, and break interrupt. the alternate vectors are in the $fe page instead of the $ff page and allow code execution from the internal monitor firmware instead of user code. table 10-1. mode selection irq1 /v pp pin pc0 pin pc1 pin pa0 pin pc3 pin mode cgmout bus frequency v dd + v hi 1011monitor cgmxclk 2 cgmout 2 v dd + v hi 1010monitor cgmxclk cgmout 2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) functional description mc68HC08KH12a ? rev. 1.0 data sheet motorola monitor rom (mon) 149 when the host computer has comple ted downloading code into the mcu ram, this code can be executed by driving pta0 low while asserting rst low and then high. the internal monitor rom fi rmware will interpret the low on pta0 as an i ndication to jump to ra m, and execution control will then continue from ram. execution of an swi from the downloaded code will return program control to the internal monitor rom firmware. alternatively, the host can send a run command, whic h executes an rti, and this can be used to send control to the addr ess on the stack pointer. the cop module is disabled in monitor mode as long as v dd +v hi is applied to either the irq1 /v pp pin or the rst pin. ( see section 7. system integration module (sim) for more informat ion on modes of operation.) table 10-2 is a summary of the differ ences between user mode and monitor mode. table 10-2. mode differences modes functions cop reset vector high reset vector low break vector high break vector low swi vector high swi vector low user enabled $fffe $ffff $fffc $fffd $fffc $fffd monitor disabled (1) 1. if the high voltage (v dd + v hi ) is removed from the irq1 /v pp pin or the rst pin, the sim asserts its cop enable output. the cop is a mask option enabled or disabled by the copd bit in the configuration register. $fefe $feff $fefc $fefd $fefc $fefd f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) data sheet mc68HC08KH12a ? rev. 1.0 150 monitor rom (mon) motorola 10.4.2 data format communication with the monitor rom is in standard non-return-to-zero (nrz) mark/space data format. (see figure 10-2 and figure 10-3 .) figure 10-2. moni tor data format figure 10-3. sample monitor waveforms the data transmit and receive rate can be anywhere fr om 4800 baud to 28.8 kbaud. transmit and receive baud rates must be identical. 10.4.3 echoing as shown in figure 10-4 , the monitor rom immediately echoes each received byte back to the pt a0 pin for error checking. figure 10-4. read transaction any result of a command appears after the ec ho of the last byte of the command. bit 5 start bit bit 0 bit 1 next stop bit start bit bit 2 bit 3 bit 4 bit 6 bit 7 bit 5 start bit bit 0 bit 1 next stop bit start bit bit 2 bit 3 bit 4 bit 6 bit 7 start bit bit 0 bit 1 next stop bit start bit bit 2 $a5 break bit 3bit 4bit 5bit 6bit 7 addr. high read read addr. high addr. low addr. low data echo sent to monitor result f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) functional description mc68HC08KH12a ? rev. 1.0 data sheet motorola monitor rom (mon) 151 10.4.4 break signal a start bit followed by nine low bits is a break signal. (see figure 10-5.) when the monitor receives a break sign al, it drives the pta0 pin high for the duration of tw o bits before echoi ng the break signal. figure 10-5. break transaction 10.4.5 commands the monitor rom uses t he following commands: read (read memory) write (write memory) iread (indexed read) iwrite (indexed write) readsp (read stack pointer) run (run user program) 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 missing stop bit two-stop-bit delay before zero echo f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) data sheet mc68HC08KH12a ? rev. 1.0 152 monitor rom (mon) motorola table 10-3. read (r ead memory) command description read byte from memory operand specifies 2-byte address in high byte:low byte order data returned returns contents of specified address opcode $4a command sequence addr. high read read addr. high addr. low addr. low data echo sent to monitor result table 10-4. write (write memory) command description write byte to memory operand specifies 2-byte address in high byte:low byte order; low byte followed by data byte data returned none opcode $49 command sequence addr. high write write addr. high addr. low addr. low data echo sent to monitor data f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) functional description mc68HC08KH12a ? rev. 1.0 data sheet motorola monitor rom (mon) 153 table 10-5. iread (i ndexed read) command description read next 2 bytes in me mory from last address accessed operand specifies 2-byte address in high byte:low byte order data returned returns contents of next two addresses opcode $1a command sequence data iread iread data echo sent to monitor result table 10-6. iwrite (indexed write) command description write to last address accessed + 1 operand specifies single data byte data returned none opcode $19 command sequence data iwrite iwrite data echo sent to monitor f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) data sheet mc68HC08KH12a ? rev. 1.0 154 monitor rom (mon) motorola note: a sequence of iread or iwrite commands can sequentially access a block of memory over the full 64-kbyte memory map. table 10-7. readsp (read stack pointer) command description reads stack pointer operand none data returned returns stack pointer in high byte:low byte order opcode $0c command sequence table 10-8. run (run u ser program) command description executes rti instruction operand none data returned none opcode $28 command sequence sp high readsp readsp sp low echo sent to monitor result run run echo sent to monitor f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) functional description mc68HC08KH12a ? rev. 1.0 data sheet motorola monitor rom (mon) 155 10.4.6 baud rate the communication baud rate is cont rolled by crystal frequency and the state of the ptc3 pin upon entry into monitor mode. when ptc3 is high, the divide by ratio is 1024. if the ptc3 pin is at logic zero upon entry into monitor mode, the divi de by ratio is 512. table 10-9. monitor baud rate selection crystal frequency (mhz) ptc3 pin baud rate 4.9152mhz 0 9600 bps 4.9152mhz 1 4800 bps f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . monitor rom (mon) data sheet mc68HC08KH12a ? rev. 1.0 156 monitor rom (mon) motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC08KH12a ? rev. 1.0 data sheet motorola timer interface module (tim) 157 data sheet ? mc68HC08KH12a section 11. timer interface module (tim) 11.1 contents 11.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 11.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 11.4 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 11.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159 11.5.1 tim counter prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 11.5.2 input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 11.5.3 output compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 11.5.3.1 unbuffered output compare . . . . . . . . . . . . . . . . . . . . . 162 11.5.3.2 buffered output com pare . . . . . . . . . . . . . . . . . . . . . . .163 11.5.4 pulse width modulatio n (pwm) . . . . . . . . . . . . . . . . . . . . . 163 11.5.4.1 unbuffered pwm sig nal generation . . . . . . . . . . . . . . . 164 11.5.4.2 buffered pwm signal generation . . . . . . . . . . . . . . . . . 165 11.5.4.3 pwm initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 11.6 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167 11.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 11.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168 11.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168 11.8 tim during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 168 11.9 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 11.9.1 tim clock pin (pte0/tc lk) . . . . . . . . . . . . . . . . . . . . . . .169 11.9.2 tim channel i/o pins (pte1/tch0:pte2/ tch1) . . . . . . . 169 11.10 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 11.10.1 tim status and control register (tsc) . . . . . . . . . . . . . . . 170 11.10.2 tim counter regist ers (tcnth:tcntl) . . . . . . . . . . . . . . 172 11.10.3 tim counter modul o registers (tmodh:tm odl) . . . . . . 173 11.10.4 tim channel status and co ntrol registers (tsc0:tsc1) . 174 11.10.5 tim channel registers (tch0h /l?tch1h/l) . . . . . . . . . . 178 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) data sheet mc68HC08KH12a ? rev. 1.0 158 timer interface module (tim) motorola 11.2 introduction this section describes the timer interface module. the tim is a two-channel timer that provides a timing refere nce with input capture, output compare, and pulse-wid th-modulation functions. figure 11-1 is a block diagram of the tim. 11.3 features features of the tim include the following: two input capture/ou tput compare channels ? rising-edge, falling-edge, or any-edge input capture trigger ? set, clear, or toggle output compare action buffered and unbuffered pulse width modulation (pwm) signal generation programmable tim clock input ? seven-frequency internal bus clock prescaler selection ? external tim clock input (bus frequency 2 maximum) free-running or modul o up-count operation toggle any channel pin on overflow tim counter stop and reset bits 11.4 pin name conventions the tim share three i/o pi ns with three port e i/ o pins. the full name of the tim i/o pin is listed in table 11-1 . the generic pin name appear in the text that follows. table 11-1. tim pi n name conventions tim generic pin names: tclk tch0 tch1 full tim pin names: pte0/tclk pte1/tch0 pte2/tch1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) functional description mc68HC08KH12a ? rev. 1.0 data sheet motorola timer interface module (tim) 159 11.5 functional description figure 11-1 shows the structure of the tim. the central component of the tim is the 16-bit tim counter that can operate as a free-running counter or a modulo up-counter. the tim counter provides the timing reference for the input capture and output co mpare functions. the tim counter modulo registers, tmodh:tmodl, contro l the modulo value of the tim counter. software can read th e tim counter value at any time without affecting the counting sequence. the two tim channels are program mable independently as input capture or output compare channels. figure 11-1. tim block diagram prescaler prescaler select 16-bit comparator ps2 ps1 ps0 16-bit comparator 16-bit latch tch0h:tch0l ms0a els0b els0a tof toie 16-bit comparator 16-bit latch tch1h:tch1l channel 0 channel 1 tmodh:tmodl trst tstop tov0 ch0ie ch0f els1b els1a tov1 ch1ie ch1max ch1f ch0max ms0b 16-bit counter internal bus ms1a tclk pte0/tclk internal bus clock pte2/tch1 pte1/tch0 interrupt logic pte2 logic interrupt logic interrupt logic pte1 logic f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) data sheet mc68HC08KH12a ? rev. 1.0 160 timer interface module (tim) motorola addr. register name bit 7654321bit 0 $0010 tim status/control register (tsc) read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset:00100000 $0012 tim counter register high (tcnth) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset:00000000 $0013 tim counter register low (tcntl) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset:00000000 $0014 tim counter modulo register high (tmodh) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset:11111111 $0015 tim counter modulo register low (tmodl) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset:11111111 $0016 tim channel 0 status and control register (tsc0) read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 $0017 tim channel 0 register high (tch0h) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset:xxxxxxxx $0018 tim channel 0 register low (tch0l) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset:xxxxxxxx $0019 tim channel 1 status and control register (tsc1) read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset:00000000 figure 11-2. tim i/o register summary f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) functional description mc68HC08KH12a ? rev. 1.0 data sheet motorola timer interface module (tim) 161 11.5.1 tim counter prescaler the tim clock source can be one of th e seven prescaler outputs or the tim clock pin, pte0/tclk. the pre scaler generates seven clock rates from the internal bus cl ock. the prescaler select bits, ps[2:0], in the tim status and control register (tsc ) select the tim clock source. 11.5.2 input capture with the input capture function, the tim can capture the time at which an external event occurs. when an acti ve edge occurs on the pin of an input capture channel, the tim latches the cont ents of the tim counter into the tim channel registers, tc hxh:tchxl. the polarity of the active edge is programmable. input captures can generate tim cpu interrupt requests. 11.5.3 output compare with the output compare function, the tim can gener ate a periodic pulse with a programmable polarity, duration, and fr equency. when the counter reaches the value in the r egisters of an output compare channel, the tim can set, clear, or toggle the channel pin. output compares can generate tim cpu interrupt requests. $001a tim channel 1 register high (tch1h) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset:xxxxxxxx $001b tim channel 1 register low (tch1l) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset:xxxxxxxx = unimplemented x = indeterminate figure 11-2. tim i/o register summary f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) data sheet mc68HC08KH12a ? rev. 1.0 162 timer interface module (tim) motorola 11.5.3.1 unbuffer ed output compare any output compare channel can generate unbuffered output compare pulses as described in 11.5.3 output compare . the pulses are unbuffered because changing the output compare value requires writing the new value over the old value currently in the tim channel registers. an unsynchronized write to the tim channel regist ers to change an output compare value could cause incorrect operati on for up to two counter overflow periods. for exampl e, writing a new value before the counter reaches the old value but after the c ounter reaches the new value prevents any compare during that counter overflow period. also, using a tim overflow interrupt rout ine to write a new, smaller output compare value may caus e the compare to be missed. the tim may pass the new value befor e it is written. use the following methods to synch ronize unbuffered changes in the output compare va lue on channel x: when changing to a smaller va lue, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current output compare pulse . the interrupt routine has until the end of the counter overflow period to write the new value. when changing to a larger output compare val ue, enable tim overflow interrupts a nd write the new value in the tim overflow interrupt routine. the tim overflow interrupt occurs at the end of the current counter overflow perio d. writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same counter overflow period. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) functional description mc68HC08KH12a ? rev. 1.0 data sheet motorola timer interface module (tim) 163 11.5.3.2 buffered output compare channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the pte1/tch0 pin. the tim channel registers of the lin ked pair alternatel y control the output. setting the ms0b bit in tim channel 0 status and control register (tsc0) links channel 0 and channel 1. the output comp are value in the tim channel 0 registers initially controls the output on t he pte1/tch0 pin. writing to the tim c hannel 1 registers enables the tim channel 1 registers to synchronously control the output after the ti m overflows. at each subsequent overflow, t he tim channel registers (0 or 1) that control the output are the ones written to last. tsc0 controls and monitors the buffered output compare function, and tim channel 1 status and control register (tsc1) is unused. while the ms0b bit is set, the channel 1 pin, pte2/tch1, is available as a general-purpose i/o pin. note: in buffered output compare operati on, do not write new output compare values to the currently active channel registers. user software should track the currently active channel to prevent writing a new value to the active channel. writing to the active channel registers is the same as generating unbuffered output compares. 11.5.4 pulse widt h modulation (pwm) by using the toggle-on-overflow f eature with an output compare channel, the tim can generate a pwm signal. the value in the tim counter modulo registers determi nes the period of th e pwm signal. the channel pin toggles when the counter reaches the value in the tim counter modulo registers. the time between ov erflows is the period of the pwm signal. as figure 11-3 shows, the output compar e value in the tim channel registers determines t he pulse width of the pwm signal. the time between overflow and output compare is the pulse width. program the tim to clear the channel pin on outpu t compare if the state of the pwm pulse is logic one. program the tim to set the pin if the state of the pwm pulse is logic zero. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) data sheet mc68HC08KH12a ? rev. 1.0 164 timer interface module (tim) motorola figure 11-3. pwm peri od and pulse width the value in the tim counter modu lo registers and the selected prescaler output determines the frequency of the pwm output. the frequency of an 8-bit pwm signal is va riable in 256 in crements. writing $00ff (255) to the ti m counter modulo regi sters produces a pwm period of 256 times the in ternal bus clock period if the prescaler select value is 000 (see 11.10.1 tim status and control register (tsc) ). the value in the tim chan nel registers determines the pulse width of the pwm output. the pulse width of an 8-bit pwm sign al is variable in 256 increments. writing $008 0 (128) to the tim c hannel registers produces a duty cycle of 128 /256 or 50%. 11.5.4.1 unbuffered pwm signal generation any output compare channel can generate unbuffered pwm pulses as described in 11.5.4 pulse width modulation (pwm) . the pulses are unbuffered because changing the pulse width requires writing the new pulse width value over the old value currentl y in the tim channel registers. an unsynchronized write to the ti m channel registers to change a pulse width value could cause incorrect oper ation for up to two pwm periods. for example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that pwm period. also, using a tim overflow inte rrupt routine to write a new, smaller pulse width value may caus e the compare to be missed. the tim may pass the new value before it is written. ptex/tchxa period pulse width overflow overflow overflow output compare output compare output compare f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) functional description mc68HC08KH12a ? rev. 1.0 data sheet motorola timer interface module (tim) 165 use the following methods to synch ronize unbuffered changes in the pwm pulse width on channel x: when changing to a shorter pulse width, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current pu lse. the interrupt routi ne has until the end of the pwm period to write the new value. when changing to a longer pulse width, enable tim overflow interrupts and write the new value in the tim overflow interrupt routine. the tim overflow interrupt occurs at the end of the current pwm period. writing a larger val ue in an output compare interrupt routine (at the end of the current pulse) c ould cause two output compares to occur in the same pwm period. note: in pwm signal generation , do not program the pw m channel to toggle on output compare. toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self-correct in the event of softw are error or noise . toggling on output compare also can cause incorr ect pwm signal generation when changing the pwm pulse width to a new, much larger value. 11.5.4.2 buffered pwm signal generation channels 0 and 1 can be linked to form a buffered pwm channel whose output appears on the pte1 /tch0 pin. the tim channel registers of the linked pair alternatel y control the pulse width of the output. setting the ms0b bit in tim channel 0 status and control register (tsc0) links channel 0 and channel 1. the tim channel 0 registers initially control the pulse width on the pte1/tch0 pin. writing to the tim channel 1 registers ena bles the tim channel 1 registers to synchronously control the pulse width at the beginning of the next pwm period. at each subsequent overflow, the tim channel registers (0 or 1) that control the pulse wi dth are the ones wr itten to last. tsc0 controls and monitors the buffered pwm func tion, and tim channel 1 status and control register (tsc1) is unused. whil e the ms0b bit is set, the channel 1 pin, pte2/tch1, is avail able as a general-purpose i/o pin. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) data sheet mc68HC08KH12a ? rev. 1.0 166 timer interface module (tim) motorola note: in buffered pwm signal gener ation, do not write new pulse width values to the currently active channel registers. user so ftware should track the currently active channel to prevent writing a new value to the active channel. writing to the active c hannel registers is the same as generating unbuffer ed pwm signals. 11.5.4.3 pwm initialization to ensure correct operation when gen erating unbuffered or buffered pwm signals, use this initialization procedure: 1. in the tim status and control register (tsc): a. stop the tim counter by se tting the tim stop bit, tstop. b. reset the tim counter and pre scaler by setting the tim reset bit, trst. 2. in the tim counter modulo regi sters (tmodh:tmodl), write the value for the required pwm period. 3. in the tim channel x registers (t chxh:tchxl), write the value for the required pulse width. 4. in tim channel x status and control register (tscx): a. write 0:1 (for unbuffered outp ut compare or pwm signals) or 1:0 (for buffered output com pare or pwm si gnals) to the mode select bits, msxb:msxa. (see table 11-3 .) b. write 1 to the toggle- on-overflow bit, tovx. c. write 1:0 (to clear output on co mpare) or 1:1 (to set output on compare) to the edge/level se lect bits, elsxb:elsxa. the output action on compare must force the output to the complement of the pulse width level. (see table 11-3 .) note: in pwm signal generation , do not program the pw m channel to toggle on output compare. toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self-correct in the event of softw are error or noise . toggling on output compare can also cause incorr ect pwm signal generation when changing the pwm pulse width to a new, much larger value. 5. in the tim status control regist er (tsc), clear t he tim stop bit, tstop. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) interrupts mc68HC08KH12a ? rev. 1.0 data sheet motorola timer interface module (tim) 167 setting ms0b links chann els 0 and 1 and configur es them for buffered pwm operation. the tim channel 0 r egisters (tch0h:tch0l) initially control the buffered pwm output. tim status contro l register 0 (tscr0) controls and monitors the pwm signal from the linked channels. ms0b takes priority over ms0a. clearing the toggle-on-ove rflow bit, tovx, inhibi ts output toggles on tim overflows. subsequent outpu t compares try to forc e the output to a state it is already in and have no effect . the result is a 0% duty cycle output. setting the channel x maximum duty cycle bit (chxmax) and setting the tovx bit generates a 100% duty cycle output. see 11.10.4 tim channel status and control registers (tsc0:tsc1) . 11.6 interrupts the following tim sources can generate interrupt requests: tim overflow flag (tof) ? th e tof bit is set when the tim counter reaches the modulo value programmed in the tim counter modulo registers. the tim overfl ow interrupt enable bit, toie, enables tim overflow cpu interr upt requests. tof and toie are in the tim status and control register. tim channel flags ( ch1f:ch0f) ? the chxf bi t is set when an input capture or output compar e occurs on channel x. channel x tim cpu interrupt requests ar e controlled by the channel x interrupt enable bit, chxie. c hannel x tim cpu interrupt requests are enabled when chxie=1. chxf and chxie ar e in the tim channel x status and control register. 11.7 low-power modes the wait and stop instruct ions put the mcu in low power-consumption standby modes. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) data sheet mc68HC08KH12a ? rev. 1.0 168 timer interface module (tim) motorola 11.7.1 wait mode the tim remains active after the executi on of a wait instru ction. in wait mode the tim registers are not accessible by the cpu. any enabled cpu interrupt request from the tim can bring the mcu out of wait mode. if tim functions are not required during wait mode, reduce power consumption by stopping the tim befor e executing the wait instruction. 11.7.2 stop mode the tim is inactive after the executi on of a stop instru ction. the stop instruction does no t affect register conditions or the state of the tim counter. tim operation resumes when the mcu exits stop mode after an external interrupt. 11.8 tim during break interrupts a break interrupt st ops the tim counter. the system integration module (sim) c ontrols whether status bits in other modules can be cleared during th e break state. the bcfe bit in the break flag control regi ster (bfcr) enables software to clear status bits during the break state. (see 8.8.3 break flag control register (bfcr) .) to allow software to clear status bi ts during a break interrupt, write a logic one to the bcfe bit. if a status bit is cleared during the break state, it remains cleared when the mcu exits the break state. to protect status bits dur ing the break state, writ e a logic zero to the bcfe bit. with bcfe at logic zero (its default state), software can read and write i/o registers during the br eak state without affecting status bits. some status bits have a two- step read/write cleari ng procedure. if software does the first step on such a bit before the brea k, the bit cannot change during the break stat e as long as bcfe is at logic zero. after the break, doing the second step clears the status bit. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) i/o signals mc68HC08KH12a ? rev. 1.0 data sheet motorola timer interface module (tim) 169 11.9 i/o signals port e shares three of its pins with the tim. pte0/tclk is and external clock input to the tim prescaler. the two tim channel i/o pins are pte1/tch0 and pte2/tch1. 11.9.1 tim clock pin (pte0/tclk) pte0/tclk is an external clock input that can be the clock source for the tim counter instead of the presca led internal bus cl ock. select the pte0/tclk input by writing logic ones to the three prescaler select bits, ps[2:0]. (see 11.10.1 tim status and control register (tsc) .) the minimum tclk pulse width, tclk lmin or tclk hmin , is: the maximum tclk frequency is: bus frequency 2 pte0/tclk is available as a general -purpose i/o pin when not used as the tim clock input. when the pte0/t clk pin is the tim clock input, it is an input regardless of the state of the ddre0 bit in data direction register e. 11.9.2 tim channel i/o pi ns (pte1/tch0 :pte2/tch1) each channel i/o pin is progr ammable independently as an input capture pin or an output compare pi n. pte1/tch0 can be configured as buffered output compare or buffered pwm pins. 11.10 i/o registers the following i/o registers control and monitor operation of the tim: tim status and control register (tsc) tim counter registers (tcnth:tcntl) tim counter modulo registers (tmodh:tmodl) tim channel status and con trol registers (tsc0 and tsc1) tim channel registers (tch 0h:tch0l and tch1h:tch1l) 1 bus frequency ------------------ ------------------- t su + f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) data sheet mc68HC08KH12a ? rev. 1.0 170 timer interface module (tim) motorola 11.10.1 tim status and co ntrol register (tsc) the tim status and control r egister does the following: enables tim overflow interrupts flags tim overflows stops the tim counter resets the tim counter prescales the tim counter clock tof ? tim overflow flag bit this read/write flag is set when t he tim counter reaches the modulo value programmed in the tim counter modulo registers. clear tof by reading the tim status and control register w hen tof is set and then writing a logic zero to tof. if anot her tim overflow oc curs before the clearing sequence is complete, then wr iting logic zero to tof has no effect. therefore, a tof interrupt request cannot be lost due to inadvertent clearing of tof. reset clears the tof bit. writing a logic one to tof has no effect. 1 = tim counter has reached modulo value 0 = tim counter has not reached modulo value toie ? tim overflow interrupt enable bit this read/write bi t enables tim overflow in terrupts when the tof bit becomes set. reset cl ears the toie bit. 1 = tim overflow interrupts enabled 0 = tim overflow interrupts disabled address: $0010 bit 7654321bit 0 read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset:00100000 = unimplemented figure 11-4. tim st atus and control register (tsc) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) i/o registers mc68HC08KH12a ? rev. 1.0 data sheet motorola timer interface module (tim) 171 tstop ? tim stop bit this read/write bit stop s the tim counter. c ounting resumes when tstop is cleared. reset sets t he tstop bit, stopping the tim counter until software clears the tstop bit. 1 = tim counter stopped 0 = tim counter active note: do not set the tstop bit before enteri ng wait mode if the tim is required to exit wait mode. trst ? tim reset bit setting this write-only bit resets the tim counter and the tim prescaler. setting trst has no ef fect on any other registers. counting resumes from $0000 . trst is cleared automatically after the tim counter is rese t and always reads as l ogic zero. reset clears the trst bit. 1 = prescaler and tim counter cleared 0 = no effect note: setting the tstop and trst bits simultaneously stops the tim counter at a value of $0000. ps[2:0] ? prescaler select bits these read/write bits select either the pte0/tclk pin or one of the seven prescaler outputs as t he input to the tim counter as table 11-2 shows. reset clear s the ps[2:0] bits. table 11-2. prescaler selection ps2 ps1 ps0 tim clock source 0 0 0 internal bus clock 1 0 0 1 internal bus clock 2 0 1 0 internal bus clock 4 0 1 1 internal bus clock 8 1 0 0 internal bus clock 16 1 0 1 internal bus clock 32 1 1 0 internal bus clock 64 111 pte0/tclk f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) data sheet mc68HC08KH12a ? rev. 1.0 172 timer interface module (tim) motorola 11.10.2 tim counter r egisters (tcnth:tcntl) the two read-only tim counter register s contain the high and low bytes of the value in the ti m counter. reading the high byte (tcnth) latches the contents of t he low byte (tcntl) into a buffer. subsequent reads of tcnth do not affect the latched tc ntl value until tcntl is read. reset clears the tim counter registers. setting the tim reset bit (trst) also clears the tim counter registers. note: if you read tcnth during a break interrupt, be sure to unlatch tcntl by reading tcntl before exiting the break interrupt. otherwise, tcntl retains the value latc hed during the break. address: $0012 tcnth bit 7654321bit 0 read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset:00000000 address: $0013 tcntl bit 7654321bit 0 read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset:00000000 = unimplemented figure 11-5. tim counter registers (tcnth:tcntl) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) i/o registers mc68HC08KH12a ? rev. 1.0 data sheet motorola timer interface module (tim) 173 11.10.3 tim counter modul o registers (tmodh:tmodl) the read/write tim modulo registers contain the modul o value for the tim counter. when the tim counter reaches t he modulo value, the overflow flag (tof) becomes set, and the tim counter resumes counting from $0000 at the next timer clock. writing to the high byte (tmodh) inhibits the tof bit and overflow inte rrupts until the low byte (tmodl) is written. reset sets the ti m counter modulo registers. note: reset the tim counter bef ore writing to the tim counter modulo registers. address: $0014 tmodh bit 7654321bit 0 read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset:11111111 address: $0015 tmodl bit 7654321bit 0 read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset:11111111 figure 11-6. tim counter modu lo registers (tmodh:tmodl) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) data sheet mc68HC08KH12a ? rev. 1.0 174 timer interface module (tim) motorola 11.10.4 tim channel st atus and control r egisters (tsc0:tsc1) each of the tim channel status and control regi sters does the following: flags input captures and output compares enables input capture and output compare interrupts selects input capture, output compare, or pwm operation selects high, low, or t oggling output on output compare selects rising edge, fall ing edge, or any edge as the active input capture trigger selects output toggl ing on tim overflow selects 0% and 1 00% pwm duty cycle selects buffered or unbuffer ed output compare/pwm operation address: $0016 tsc0 bit 7654321bit 0 read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 address: $0019 tsc1 bit 7654321bit 0 read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset:00000000 = unimplemented figure 11-7. tim channel st atus and control registers (tsc0:tsc1) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) i/o registers mc68HC08KH12a ? rev. 1.0 data sheet motorola timer interface module (tim) 175 chxf ? chann el x flag bit when channel x is an inpu t capture channel, this read/write bit is set when an active edge occurs on the channel x pin. when channel x is an output compare channel, chxf is set when the value in the tim counter registers matche s the value in the ti m channel x registers. when tim cpu interrupt requests are enabled (chxie=1), clear chxf by reading the tim channel x status an d control register with chxf set and then writing a logic zero to chxf. if another interrupt request occurs before the clearing sequence is complete, then writing logic zero to chxf has no effe ct. therefore, an interrupt request cannot be lost due to inadver tent clearing of chxf. reset clears the chxf bit. writing a logic one to chxf has no effect. 1 = input capture or out put compare on channel x 0 = no input capture or output compare on channel x chxie ? channel x in terrupt enable bit this read/write bi t enables tim cpu interrupt service requests on channel x. reset cl ears the chxie bit. 1 = channel x cpu inte rrupt requests enabled 0 = channel x cpu interr upt requests disabled msxb ? mode select bit b this read/write bit sele cts buffered output co mpare/pwm operation. msxb exists only in the tim channel 0 status and control register. setting ms0b disables the channel 1 status and control register and reverts tch1 to gen eral-purpose i/o. reset clears the msxb bit. 1 = buffered output com pare/pwm operation enabled 0 = buffered output compar e/pwm operation disabled msxa ? mode select bit a when elsxb:elsxa 0:0, this read/write bi t selects either input capture operation or unbuffered output compare/pwm operation. (see table 11-3 .) 1 = unbuffered output compare/pwm operation 0 = input capt ure operation f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) data sheet mc68HC08KH12a ? rev. 1.0 176 timer interface module (tim) motorola when elsxb:elsxa = 0:0, this read/wr ite bit selects the initial output level of the tchx pin. (see table 11-3 .) reset clears the msxa bit. 1 = initial output level low 0 = initial output level high note: before changing a channel function by writing to the msxb or msxa bit, set the tstop and trst bi ts in the tim status and control register (tsc). elsxb and elsxa ? edge/level select bits when channel x is an i nput capture channel, th ese read/write bits control the active edge- sensing logic on channel x. when channel x is an output co mpare channel, elsxb and elsxa control the channel x output beh avior when an output compare occurs. when elsxb and elsxa are both cl ear, channel x is not connected to port e, and pin ptex/tchx is av ailable as a gener al-purpose i/o pin. table 11-3 shows how elsxb and elsxa work. reset clears the elsxb and elsxa bits. table 11-3. mode, edge, and level selection msxb msxa elsxb elsxa mode configuration x000 output preset pin under port control; initial output level high x100 pin under port control; initial output level low 0001 input capture capture on rising edge only 0 0 1 0 capture on falling edge only 0 0 1 1 capture on rising or falling edge 0101 output compare or pwm toggle output on compare 0 1 1 0 clear output on compare 0 1 1 1 set output on compare 1 x 0 1 buffered output compare or buffered pwm toggle output on compare 1 x 1 0 clear output on compare 1 x 1 1 set output on compare f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) i/o registers mc68HC08KH12a ? rev. 1.0 data sheet motorola timer interface module (tim) 177 note: before enabling a tim ch annel register for input capture operation, make sure that the ptex/tch x pin is stable for at least two bus clocks. tovx ? toggle-on-overflow bit when channel x is an output compar e channel, this read/write bit controls the behavior of the channel x output when t he tim counter overflows. when channel x is an i nput capture channel, tovx has no effect. reset clear s the tovx bit. 1 = channel x pin toggle s on tim counter overflow 0 = channel x pin does not t oggle on tim counter overflow note: when tovx is set, a tim counter overflow takes precedence over a channel x output compare if bot h occur at the same time. chxmax ? channel x ma ximum duty cycle bit when the tovx bit is at logic one, setting the chxmax bit forces the duty cycle of buffered and unbuffe red pwm signals to 100%. as figure 11-8 shows, the chxmax bit takes effect in the cycle after it is set or cleared. the output stays at the 100% duty cycle level until the cycle after chxmax is cleared. figure 11-8. chxmax latency output overflow ptex/tchx period chxmax overflow overflow overflow overflow compare output compare output compare output compare f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer interface module (tim) data sheet mc68HC08KH12a ? rev. 1.0 178 timer interface module (tim) motorola 11.10.5 tim channel regi sters (tch0h/l?tch1h/l) these read/write registers contain the captured tim counter value of the input capture function or the outp ut compare value of the output compare function. the state of the tim channel register s after reset is unknown. in input capture mode (m sxb:msxa = 0:0), reading the high byte of the tim channel x registers (t chxh) inhibits input c aptures until the low byte (tchxl) is read. in output compare mode (msxb:msxa 0:0), writing to the high byte of the tim channel x regist ers (tchxh) inhibits out put compares until the low byte (tchxl) is written. address: $0017 tch0h bit 7654321bit 0 read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset: indeterminate after reset address: $0018 tch0l bit 7654321bit 0 read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset: indeterminate after reset address: $001a tch1h bit 7654321bit 0 read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset: indeterminate after reset address: $001b tch1l bit 7654321bit 0 read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset: indeterminate after reset figure 11-9. tim channel regi sters (tch0h/l:tch1h/l) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC08KH12a ? rev. 1.0 data sheet motorola input/output (i/o) ports 179 data sheet ? mc68HC08KH12a section 12. input/output (i/o) ports 12.1 contents 12.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 12.3 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 12.3.1 port a data register (pta) . . . . . . . . . . . . . . . . . . . . . . . . 182 12.3.2 data direction register a (ddra) . . . . . . . . . . . . . . . . . . . 182 12.4 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 12.4.1 port b data register (ptb) . . . . . . . . . . . . . . . . . . . . . . . . 184 12.4.2 data direction register b (ddrb) . . . . . . . . . . . . . . . . . . . 185 12.5 port c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 12.5.1 port c data register (ptc) . . . . . . . . . . . . . . . . . . . . . . . . 186 12.5.2 data direction register c (ddrc). . . . . . . . . . . . . . . . . . . 187 12.6 port d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 12.6.1 port d data register (ptd) . . . . . . . . . . . . . . . . . . . . . . . . 189 12.6.2 data direction register d (ddrd). . . . . . . . . . . . . . . . . . . 189 12.7 port e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 12.7.1 port e data register (pte) . . . . . . . . . . . . . . . . . . . . . . . . 191 12.7.2 data direction register e (ddre) . . . . . . . . . . . . . . . . . . . 192 12.7.3 port-e optical interface enable register . . . . . . . . . . . . . . 194 12.8 port f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 12.8.1 port f data register (ptf) . . . . . . . . . . . . . . . . . . . . . . . . 198 12.8.2 data direction register f (ddrf) . . . . . . . . . . . . . . . . . . . 199 12.9 port options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 12.9.1 port option control register (poc) . . . . . . . . . . . . . . . . . . 200 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports data sheet mc68HC08KH12a ? rev. 1.0 180 input/output (i/o) ports motorola 12.2 introduction forty-two bidirectional inpu t-output (i/o) pins form five parallel ports. all i/o pins are programmab le as inputs or outputs. note: connect any unused i/o pins to an appr opriate logic level, either v dd or v ss . although the i/o port s do not require te rmination for proper operation, termination reduces e xcess current consumption and the possibility of el ectrostatic damage. table 12-1. i/o port register summary addr. register name bit 7654321bit 0 $0000 port a data register (pta) read: pta7 pta6 pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset $0001 port b data register (ptb) read: ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: reset: unaffected by reset $0002 port c data register (ptc) read: 0 0 0 ptc4 ptc3 ptc2 ptc1 ptc0 write: reset: unaffected by reset $0003 port d data register (ptd) read: ptd7 ptd6 ptd5 ptd4 ptd3 ptd2 ptd1 ptd0 write: reset: unaffected by reset $0004 data direction register a (ddra) read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset:00000000 $0005 data direction register b (ddrb) read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset:00000000 $0006 data direction register c (ddrc) read: 0 0 0 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 write: reset:00000000 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports introduction mc68HC08KH12a ? rev. 1.0 data sheet motorola input/output (i/o) ports 181 $0007 data direction register d (ddrd) read: ddrd7 ddrd6 ddrd5 ddrd4 ddrd3 ddrd2 ddrd1 ddrd0 write: reset:00000000 $0008 port e data register (pte) read: 0 0 0 pte4 pte3 pte2 pte1 pte0 write: reset: unaffected by reset $0009 port f data register (ptf) read: ptf7 ptf6 ptf5 ptf4 ptf3 ptf2 ptf1 ptf0 write: reset: unaffected by reset $000a data direction register e (ddre) read: 0 0 0 ddre4 ddre3 ddre2 ddre1 ddre0 write: reset:00000000 $000b data direction register f (ddrf) read: ddrf7 ddrf6 ddrf5 ddrf4 ddrf3 ddrf2 ddrf1 ddrf0 write: reset:00000000 $001c port e optical interface enable register (eoier) read: yref2 yref1 yref0 xref2 xref1 xref0 oiey oiex write: reset:01001000 $001d port option control register (poc) read: 0 0 ldd 00 pcp pbp pap write: reset:00100000 = unimplemented f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports data sheet mc68HC08KH12a ? rev. 1.0 182 input/output (i/o) ports motorola 12.3 port a port a is an 8-bit gener al-purpose bidirectional i/o port with software configurable pullups. 12.3.1 port a data register (pta) the port a data regist er contains a data latch fo r each of the eight port a pins. pta[7:0] ? port a data bits these read/write bits are software programmable. data direction of each port a pin is under the control of the corresponding bit in data direction register a. reset has no effect on port a data. the port a pullup enable bit, pap, in the port option control register (poc) enables pullups on port a pins if the res pective pin is configured as an input. (see 12.9 port options .) 12.3.2 data directio n register a (ddra) data direction register a determine s whether each port a pin is an input or an output. writing a l ogic one to a ddra bit enabl es the output buffer for the corresponding port a pin; a logic zero di sables the output buffer. address: $0000 bit 7654321bit 0 read: pta7 pta6 pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset figure 12-1. port a data register (pta) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports port a mc68HC08KH12a ? rev. 1.0 data sheet motorola input/output (i/o) ports 183 ddra[7:0] ? data dire ction register a bits these read/write bits control port a data direction. reset clears ddra[7:0], configuring all port a pins as inputs. 1 = corresponding port a pin configured as output 0 = corresponding port a pin configured as input note: avoid glitches on port a pi ns by writing to the port a data register before changing data direction regist er a bits fr om 0 to 1. figure 12-3 shows the port a i/o logic. figure 12-3. port a i/o circuit when bit ddrax is a lo gic one, reading address $0000 reads the ptax data latch. when bit ddrax is a logic zero, reading address $0000 reads the voltage level on the pin. the data latch can al ways be written, regardless of the state of its data direction bit. table 12-2 summarizes the operation of the port a pins. address: $0004 bit 7654321bit 0 read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset:00000000 figure 12-2. data direct ion register a (ddra) read ddra ($0004) write ddra ($0004) reset write pta ($0000) read pta ($0000) ptax ddrax ptax internal data bus f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports data sheet mc68HC08KH12a ? rev. 1.0 184 input/output (i/o) ports motorola 12.4 port b port b is an 8-bit gener al-purpose bidirectional i/o port with software configurable pullups. 12.4.1 port b data register (ptb) the port b data register co ntains a data latch for each of the eight port b pins. ptb[7:0] ? port b data bits these read/write bits are software-p rogrammable. data direction of each port b pin is under the control of the corresponding bit in data direction register b. reset has no effect on port b data. the port b pullup enable bit, pbp, in the port option control register (poc) enables pullups on port b pins if the res pective pin is configured as an input. (see 12.9 port options .). table 12-2. port a pin functions ddra bit pta bit i/o pin mode accesses to ddra accesses to pta read/write read write 0x (1) input, hi-z (2) ddra[7:0] pin pta[7:0] (3) 1 x output ddra[7:0] pta[7:0] pta[7:0] 1. x = don?t care 2. hi-z = high impedance 3. writing affects data register, but does not affect input. address: $0001 bit 7654321bit 0 read: ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: reset: unaffected by reset figure 12-4. port b data register (ptb) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports port b mc68HC08KH12a ? rev. 1.0 data sheet motorola input/output (i/o) ports 185 12.4.2 data directio n register b (ddrb) data direction register b determine s whether each port b pin is an input or an output. writing a l ogic one to a ddrb bit enabl es the output buffer for the corresponding port b pin; a logic zero di sables the output buffer. ddrb[7:0] ? data dire ction register b bits these read/write bits control port b data direction. reset clears ddrb[7:0], configuring all port b pins as inputs. 1 = corresponding port b pin configured as output 0 = corresponding port b pin configured as input note: avoid glitches on port b pi ns by writing to the port b data register before changing data direction regist er b bits fr om 0 to 1. figure 12-6 shows the port b i/o logic. figure 12-6. port b i/o circuit address: $0005 bit 7654321bit 0 read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset:00000000 figure 12-5. data direct ion register b (ddrb) read ddrb ($0005) write ddrb ($0005) reset write ptb ($0001) read ptb ($0001) ptbx ddrbx ptbx internal data bus f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports data sheet mc68HC08KH12a ? rev. 1.0 186 input/output (i/o) ports motorola when bit ddrbx is a lo gic one, reading address $0001 reads the ptbx data latch. when bit ddrbx is a logic zero, reading address $0001 reads the voltage level on the pin. the data latch can al ways be written, regardless of the state of its data direction bit. table 12-3 summarizes the operation of the port b pins. 12.5 port c port c is a 5-bit general-purpose bidi rectional i/o port with software configurable pullups and current drive options. 12.5.1 port c data register (ptc) the port c data register contains a data latch for each of the five port c pins. table 12-3. port b pin functions ddrb bit ptb bit i/o pin mode accesses to ddrb accesses to ptb read/write read write 0x (1) 1. x = don?t care input, hi-z (2) 2. hi-z = high impedance ddrb[7:0] pin ptb[7:0] (3) 3. writing affects data register, but does not affect input. 1 x output ddrb[7:0] ptb[7:0] ptb[7:0] address: $0002 bit 7654321bit 0 read: 0 0 0 ptc4 ptc3 ptc2 ptc1 ptc0 write: reset: unaffected by reset = unimplemented figure 12-7. port c data register (ptc) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports port c mc68HC08KH12a ? rev. 1.0 data sheet motorola input/output (i/o) ports 187 ptc[4:0] ? port c data bits these read/write bits are software-p rogrammable. data direction of each port c pin is under the control of the corresponding bit in data direction register c. reset has no effect on port c data. the port c pullup enable bit, pcp, in the port option control register (poc) enables pullups on por t c pins if the respective pin is configured as an input. (see 12.9 port options .) the led direct drive bit, ldd, in the port option control register (poc) controls the drive options for port c. 12.5.2 data directio n register c (ddrc) data direction register c determines whether eac h port c pin is an input or an output. writing a logic one to a ddrc bit enables the output buffer for the corresponding port c pin; a logic zero disabl es the output buffer. ddrc[4:0] ? data dire ction register c bits these read/write bits control port c data direction. reset clears ddrc[4:0], configuring all port c pins as inputs. 1 = corresponding port c pin configured as output 0 = corresponding port c pin configured as input note: avoid glitches on port c pins by writ ing to the port c dat a register before changing data direction regist er c bits fr om 0 to 1. figure 12-9 shows the port c i/o logic. address: $0006 bit 7654321bit 0 read: 0 0 0 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 write: reset:00000000 = unimplemented figure 12-8. data direct ion register c (ddrc) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports data sheet mc68HC08KH12a ? rev. 1.0 188 input/output (i/o) ports motorola figure 12-9. port c i/o circuit when bit ddrcx is a logic one, r eading address $0002 reads the ptcx data latch. when bit ddrcx is a logic zero, reading address $0002 reads the voltage level on the pin. the data latch can al ways be written, regardless of the state of its data direction bit. table 12-4 summarizes the operation of the port c pins. 12.6 port d port d is an 8-bit general -purpose bidirectional i/o port that shares its pins with the keyboard interrupt modul e (kbi). all port d pins have built- in schmitt triggered input. table 12-4. port c pin functions ddrc bit ptc bit i/o pin mode accesses to ddrc accesses to ptc read/write read write 0x (1) 1. x = don?t care input, hi-z (2) 2. hi-z = high impedance ddrc[4:0] pin ptc[4:0] (3) 3. writing affects data register, but does not affect input. 1 x output ddrc[4:0] ptc[4:0] ptc[4:0] read ddrc ($0006) write ddrc ($0006) reset write ptc ($0002) read ptc ($0002) ptcx ddrcx ptcx internal data bus f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports port d mc68HC08KH12a ? rev. 1.0 data sheet motorola input/output (i/o) ports 189 12.6.1 port d data register (ptd) the port d data register c ontains a data latch for each of the eight port d pins. ptd[7:0] ? port d data bits these read/write bits are software programmable. data direction of each port d pin is under control of the corresponding bit in data direction register d. reset has no effect on port d data. the port d pullups are automatically enabled if the resp ective pin is configured as a keyboa rd interrupt. (see 15.4.1 port-d keyboard interrupt functi onal description .) the port-d keyboard interr upt enable bits, kbdi e7?kbdie0, in the port-d keyboard interrupt enable register (kbd ier), enable the port d pins as external interrupt pins. see section 15. ke yboard interrupt module (kbi) . 12.6.2 data directio n register d (ddrd) data direction register d determines whether eac h port d pin is an input or an output. writing a logic one to a ddrd bit enables the output buffer for the corresponding port d pin; a l ogic zero disables the output buffer. address: $0003 bit 7654321bit 0 read: ptd7 ptd6 ptd5 ptd4 ptd3 ptd2 ptd1 ptd0 write: reset: unaffected by reset alternate function: kbd7 kbd6 kbd5 kbd4 kbd3 kbd2 kbd1 kbd0 figure 12-10. port d da ta register (ptd) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports data sheet mc68HC08KH12a ? rev. 1.0 190 input/output (i/o) ports motorola ddrd[7:0] ? data dire ction register d bits these read/write bits control port d data direction. reset clears ddrd[7:0], configuring all port d pins as inputs. 1 = corresponding port d pin configured as output 0 = corresponding port d pin configured as input note: avoid glitches on port d pins by writ ing to the port d dat a register before changing data direction regist er d bits fr om 0 to 1. figure 12-12 shows the port d i/o logic. figure 12-12. port d i/o circuit when bit ddrdx is a logic one, r eading address $0003 reads the ptdx data latch. when bit ddrdx is a logic zero, reading address $0003 reads the voltage level on the pin. the data latch can al ways be written, regardless of the state of its data direction bit. table 12-5 summarizes the operation of the port d pins. address: $0007 bit 7654321bit 0 read: ddrd7 ddrd6 ddrd5 ddrd4 ddrd3 ddrd2 ddrd1 ddrd0 write: reset:00000000 figure 12-11. data direct ion register d (ddrd) read ddrd ($0007) write ddrd ($0007) reset write ptd ($0003) read ptd ($0003) ptdx ddrdx ptdx internal data bus f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports port e mc68HC08KH12a ? rev. 1.0 data sheet motorola input/output (i/o) ports 191 12.7 port e port e is a 5-bit special function port t hat shares four of its pins with the keyboard interrupt module (kbi) and sh ares three of its pins with the timer interface module (tim). pt e3?pte0 pins have built-in schmitt triggered input and so ftware configurable pull-up; in addition, pte3?pte0 pins have built-in optical interface circuit which can be enabled via the port-e optical interfac e enable register. 12.7.1 port e data register (pte) the port e data register contains a data latch for each of the five port e pins. table 12-5. port d pin functions ddrd bit ptd bit i/o pin mode accesses to ddrd accesses to ptd read/write read write 0x (1) input, hi-z (2) ddrd[7:0] pin ptd[7:0] (3) 1 x output ddrd[7:0] ptd[7:0] ptd[7:0] 1. x = don?t care 2. hi-z = high impedance 3. writing affects data register, but does not affect input. address: $0008 bit 7654321bit 0 read: 0 0 0 pte4 pte3 pte2 pte1 pte0 write: reset: unaffected by reset = unimplemented alternate function: kbe3 kbe2 kbe1 kbe0 alternate function: tch1 tch0 tclk figure 12-13. port e da ta register (pte) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports data sheet mc68HC08KH12a ? rev. 1.0 192 input/output (i/o) ports motorola pte[4:0] ? port e data bits pte[4:0] are read/write, software- programmable bits. data direction of each port e pin is under the control of the co rresponding bit in data direction register e. tch1-tch0 ? timer channel i/o bits the pte2/tch1-pte1/tch0 pins ar e the tim input capture/output compare pins. the edge/le vel select bits, elsxb and elsxa, determine whether the pte2/tch 1?pte1/tch0 pins are timer channel i/o pins or general-purpose i/o pins. see section 11. timer interface module (tim) . note: data direction register e (ddre) does not affect the data direction of port e pins that are being used by the tim. however, the ddre bits always determine whether reading port e return s the states of the latches or the stat es of the pins. tclk ? timer clock input the pte0/tclk pin is the external clock input fo r the tim. the prescaler select bits, ps2-ps0, selects pe0/tc lk as the tim clock input. when not selected as the ti m clock, pe0/tclk is available for general purpose i/o. see section 11. timer in terface module (tim) . the pepe[3:0] bits in the port e ke yboard interrupt enable register enable individual pull-ups on port e pins pte3?pte 0 if the respective pin is configured as an input. (see 15.5.3.2 port-e keyboard interrupt enable register .) the port-e keyboard interrupt enable bits, kbeie3?kbeie0, in the port- e keyboard interrupt enable register (kbeier), enabl e the port e pins as external interrupt pins. see section 15. keyboard interrupt module (kbi) . 12.7.2 data directio n register e (ddre) data direction register e determine s whether each port e pin is an input or an output. writing a l ogic one to a ddre bit enabl es the output buffer for the correspondi ng port e pin; a logic zero disables the output buffer. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports port e mc68HC08KH12a ? rev. 1.0 data sheet motorola input/output (i/o) ports 193 ddre[4:0] ? data dire ction register e bits these read/write bits control port e data direction. reset clears ddre[4:0], configuring all port e pins as inputs. 1 = corresponding port e pin configured as output 0 = corresponding port e pin configured as input note: avoid glitches on port e pi ns by writing to the port e data register before changing data direction regist er e bits fr om 0 to 1. figure 12-15 shows the port e i/o logic. figure 12-15. port e i/o circuit when bit ddrex is a lo gic one, reading address $0008 reads the ptex data latch. when bit ddrex is a logic zero, reading address $0008 reads the voltage level on the pin. the data latch can al ways be written, regardless of the state of its data direction bit. table 12-4 summarizes the operation of the port e pins. address: $000a bit 7654321bit 0 read: 0 0 0 ddre4 ddre3 ddre2 ddre1 ddre0 write: reset:00000000 = unimplemented figure 12-14. data direct ion register e (ddre) read ddre ($000a) write ddre ($000a) reset write pte ($0008) read pte ($0008) ptex ddrex ptex internal data bus f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports data sheet mc68HC08KH12a ? rev. 1.0 194 input/output (i/o) ports motorola 12.7.3 port-e optical interface enable register port e pins pte3?pte0, each has an optical c oupling interface circuit which is specially built for optical mouse application. bits [1:0] of the optical interface enable register enable or disable the interface circuit in each port e pins pte3?pte0, whilst bi ts [7:2] define the reference level for the optical interface ci rcuit for optimum performance. oiex ? optical interface enable x. this enables optical interface on pte0 and pte1 pins. it also enables the voltage divider circuit. 1 = pte0 and pte1 optic al interface enabled. 0 = pte0 and pte1 optic al interface disabled. oiey ? optical interface enable y. this enables optical interface on pte2 and pte3 pins. it also enables the voltage divider circuit. 1 = pte2 and pte3 optic al interface enabled. 0 = pte2 and pte3 optic al interface disabled. table 12-6. port e pin functions ddre bit pte bit i/o pin mode accesses to ddre accesses to pte read/write read write 0x (1) input, hi-z (2) ddre[4:0] pin pte[4:0] (3) 1 x output ddre[4:0] pte[4:0] pte[4:0] 1. x = don?t care 2. hi-z = high impedance 3. writing affects data register, but does not affect input. address: $001c bit 7654321bit 0 read: yref2 yref1 yref0 xref2 xref1 xref0 oiey oiex write: reset:01001000 figure 12-16. optical interface enable register e (eoier) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports port e mc68HC08KH12a ? rev. 1.0 data sheet motorola input/output (i/o) ports 195 xref2?xref0 ? reference voltage selection x these bits sets the slicing refer ence voltage for optical interface associated with pte0 and pte1. yref2?yref0 ? reference voltage selection y these bits sets the slicing refer ence voltage for optical interface associated with pte2 and pte3. xref[2:0] / yref[2:0] pte0-pte1 / pte2-pte3 reference voltage (mv) 0200 1300 2400 3500 4600 5700 6800 7900 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports data sheet mc68HC08KH12a ? rev. 1.0 196 input/output (i/o) ports motorola figure 12-17. optical in terface voltage references x-vref voltage divider enable voltage selector y-vref voltage selector y - reference x - reference yref2 yref1 yref0 xref2 xref1 xref0 oiey oiex optical interface register ($001c) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports port e mc68HC08KH12a ? rev. 1.0 data sheet motorola input/output (i/o) ports 197 figure 12-18. port e op tical coupling interface pte0 port logic pte0 optical interface output buffer mux select pte1 port logic pte1 optical interface output buffer x-vref oiex (bit0 of $1c) 0 1 mux select 0 1 internal data bus pte2 port logic pte2 optical interface output buffer mux select pte3 port logic pte3 optical interface output buffer y-vref oiey (bit1 of $1c) 0 1 mux select 0 1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports data sheet mc68HC08KH12a ? rev. 1.0 198 input/output (i/o) ports motorola 12.8 port f port f is an 8-bit general-purpose bidi rectional i/o port that shares its pins with the keyboard in terrupt module (kbi). all port f pins have built- in schmitt triggered input and software configurable pull-up. 12.8.1 port f da ta register (ptf) the port f data register contains a data latch for each of the eight port f pins. ptf[7:0] ? port f data bits these read/write bits are software programmable. data direction of each port f pin is under the control of the correspondi ng bit in data direction register f. rese t has no effect on port f data. the port-f keyboard interr upt enable bits, kbfi e7?kbfie0, in the port-f keyboard interrupt enable r egister (kbfier), enable the port f pins as external interrupt pins. see section 15. keyboard interrupt module (kbi) . the pfpe[7:0] bits in the port f ke yboard pull-up enabl e register enable individual pull-ups on port f pins if the respective pin is configured as an input. (see 15.6.3.3 port-f pull -up enable register .) address: $0009 bit 7654321bit 0 read: ptf7 ptf6 ptf5 ptf4 ptf3 ptf2 ptf1 ptf0 write: reset: unaffected by reset alternate function: kbf7 kbf6 kbf5 kbf4 kbf3 kbf2 kbf1 kbf0 figure 12-19. port f data register (ptf) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports port f mc68HC08KH12a ? rev. 1.0 data sheet motorola input/output (i/o) ports 199 12.8.2 data directio n register f (ddrf) data direction register f determines whether each port f pin is an input or an output. writing a logic one to a ddrf bit enables the output buffer for the corresponding port f pin; a logic zero dis ables the output buffer. ddrf[7:0] ? data direction register f bits these read/write bits control port f data direction. reset clears ddrf[7:0], configuring a ll port f pins as inputs. 1 = corresponding port f pi n configured as output 0 = corresponding port f pi n configured as input note: avoid glitches on port f pins by writ ing to the port f dat a register before changing data direction regist er f bits from 0 to 1. figure 12-3 shows the port f i/o logic. figure 12-21. port f i/o circuit address: $000b bit 7654321bit 0 read: ddrf7 ddrf6 ddrf5 ddrf4 ddrf3 ddrf2 ddrf1 ddrf0 write: reset:00000000 figure 12-20. data dir ection register f (ddrf) read ddrf ($000b) write ddrf ($000b) reset write ptf ($0009) read ptf ($0009) ptfx ddrfx ptfx internal data bus f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports data sheet mc68HC08KH12a ? rev. 1.0 200 input/output (i/o) ports motorola when bit ddrfx is a logic one, reading address $0009 re ads the ptfx data latch. when bit ddrf x is a logic zero, r eading address $0009 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 12-7 summarizes the operation of the port f pins. 12.9 port options all pins of port a, port b and port c have programmable pullup resistors. port c also has le d drive capability. 12.9.1 port option c ontrol register (poc) the pullup option for each port is contro lled by one bit in the port option control register. one bi t controls the led driv e configuration on port c. table 12-7. port f pin functions ddre bit pte bit i/o pin mode accesses to ddre accesses to pte read/write read write 0x (1) 1. x = don?t care input, hi-z (2) 2. hi-z = high impedance ddrf[7:0] pin ptf[7:0] (3) 3. writing affects data register, but does not affect input. 1 x output ddrf[7:0] ptf[7:0] ptf[7:0] address: $001d bit 7654321bit 0 read: 0 0 ldd 00 pcp pbp pap write: reset:00100000 = unimplemented figure 12-22. port option control register (poc) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports port options mc68HC08KH12a ? rev. 1.0 data sheet motorola input/output (i/o) ports 201 ldd ? led direct drive control this read/write bit cont rols the output current capability of port c. when set, the port c pins have curr ent limiting ability so that a led can be connected directly between the port pin and v dd or v ss without the need of a series resistor. 1 = when respective port is confi gured as an output, make port c become current limiti ng 3 ma source/10 ma sink port pins 0 = configure port c to beco me standard i/o port pins pcp ? port c pullup enable this read/write bit controls the pullup option for port c[7:0] if its respective port pin is configured as an input. 1 = configure port c to have internal pullups 0 = disconnect port c internal pullups pbp ? port b pullup enable this read/write bit controls the pullup option for th e eight bits of port b if its respective port pi n is configured as an input. 1 = configure port b to have internal pullups 0 = disconnect port b internal pullups pap ? port a pullup enable this read/write bit controls the pullup option for th e eight bits of port a if its respective port pi n is configured as an input. 1 = configure port a to have internal pullups 0 = disconnect port a internal pullups f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports data sheet mc68HC08KH12a ? rev. 1.0 202 input/output (i/o) ports motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC08KH12a ? rev. 1.0 data sheet motorola computer operating properly (cop) 203 data sheet ? mc68HC08KH12a section 13. computer operating properly (cop) 13.1 contents 13.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 13.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204 13.4 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 13.4.1 cgmxclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205 13.4.2 copctl write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205 13.4.3 power-on reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 13.4.4 internal reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 13.4.5 reset vector fetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 13.4.6 copd (cop disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 13.4.7 coprs (cop rate sele ct) . . . . . . . . . . . . . . . . . . . . . . . . 206 13.5 cop control register (copctl) . . . . . . . . . . . . . . . . . . . . . . 207 13.6 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207 13.7 monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207 13.8 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 13.8.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208 13.8.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208 13.9 cop module during break mode . . . . . . . . . . . . . . . . . . . . . . 208 13.2 introduction this section describes the computer operating properly module, a free- running counter that ge nerates a reset if allowed to overflow. the cop module helps software recover from runaway code. prevent a cop reset by periodically clearing the cop counter. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . computer operating properly (cop) data sheet mc68HC08KH12a ? rev. 1.0 204 computer operating properly (cop) motorola 13.3 functional description figure 13-1 shows the structure of the cop module. figure 13-1. cop block diagram copctl write cgmxclk reset vector fetch reset circuit reset status register internal reset sources 12-bit sim counter clear all stages 6-bit cop counter cop disable reset copctl write clear cop module copen (from sim) cop counter cop clock cop timeout stop instruction (copd from config) cop rate sel (coprs from config) clear stages 5?12 table 13-1. cop i/o po rt register summary addr. register name bit 7654321bit 0 $001f configuration register (config) ? read: 0000 ssrec coprs stop copd write: reset:00000000 $ffff cop control register (copctl) read: low byte of reset vector write: clear cop counter reset: unaffected by reset ? one-time writable register = unimplemented f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . computer operating properly (cop) i/o signals mc68HC08KH12a ? rev. 1.0 data sheet motorola computer operating properly (cop) 205 the cop counter is a fr ee-running 6-bit counter preceded by the 12-bit sim counter. if not cleared by soft ware, the cop count er overflows and generates an asynchr onous reset after 2 18 ?2 4 or 2 13 ?2 4 cgmxclk cycles, depending on the setting of the cop rate select bit, coprs, in the configuration r egister. with a 2 18 ?2 4 cgmxclk cycle overflow option, a 6mhz crystal gives a cop tim eout period of 43.688ms. writing any value to location $ffff before an overflow occurs prevents a cop reset by clearing the cop counter and stages 12 through 5 of the sim counter. note: service the cop immediately after re set and before entering or after exiting stop mode to guarantee the ma ximum time before the first cop counter overflow. a cop reset pulls the rst pin low for 32 cgm xclk cycles and sets the cop bit in the reset st atus register (rsr) (see 7.8.2 reset status register (rsr) ). note: place cop clearing instructions in the main program and not in an interrupt subroutine. su ch an interrupt subrout ine could keep the cop from generating a reset even while the main pr ogram is not working properly. 13.4 i/o signals the following paragraphs descri be the signals shown in figure 13-1 . 13.4.1 cgmxclk cgmxclk is the crystal oscillator output si gnal. cgmxclk frequency is equal to the crystal frequency. 13.4.2 copctl write writing any value to the cop control register (copctl) (see 13.5 cop control register (copctl) ) clears the cop counter and clears bits 12 through 4 of the sim c ounter. reading the cop cont rol register returns the low byte of the reset vector. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . computer operating properly (cop) data sheet mc68HC08KH12a ? rev. 1.0 206 computer operating properly (cop) motorola 13.4.3 power-on reset the power-on reset (por) ci rcuit in the sim clears the sim counter 4096 cgmxclk cycles after power-up. 13.4.4 internal reset an internal reset clears the sim counter and the cop counter. 13.4.5 reset vector fetch a reset vector fetch occurs when the vector addres s appears on the data bus. a reset vector fetch clears the sim counter. 13.4.6 copd (cop disable) the copd signal reflec ts the state of the cop di sable bit (copd) in the configuration regist er (config). (see figure 13-2 . configuration register (config) .) 13.4.7 coprs (cop rate select) the coprs signal reflects the state of the cop ra te select bit (coprs) in the configurati on register. (see figure 13-2 . config uration register (config) .) address: $001f bit 7654321bit 0 read: 0 0 0 0 ssrec coprs stop copd write: reset:00000000 = unimplemented this is a write-once after reset register. (see section 5. configuration register (config) .) figure 13-2. configura tion register (config) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . computer operating properly (cop) cop control register (copctl) mc68HC08KH12a ? rev. 1.0 data sheet motorola computer operating properly (cop) 207 coprs ? cop rate select bit coprs selects the cop timeout period. rese t clears coprs. 1 = cop reset cycle is (2 13 ?2 4 ) cgmxclk 0 = cop reset cycle is (2 18 ?2 4 ) cgmxclk copd ? cop disable bit copd disables the cop module. 1 = cop module disabled 0 = cop module enabled 13.5 cop control register (copctl) the cop control register is locat ed at address $ffff and overlaps the reset vector. writing any value to $ffff clears t he cop counter and starts a new timeout per iod. reading location $ffff returns the low byte of the reset vector. 13.6 interrupts the cop does not generate cpu interrupt requests. 13.7 monitor mode the cop is disabled in monitor mode when v dd +v hi is present on the irq1 /v pp pin or on the rst pin. address: $ffff bit 7654321bit 0 read: low byte of reset vector write: clear cop counter reset: unaffected by reset figure 13-3. cop cont rol register (copctl) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . computer operating properly (cop) data sheet mc68HC08KH12a ? rev. 1.0 208 computer operating properly (cop) motorola 13.8 low-power modes the wait and stop in structions put the mcu in low-power consumption standby modes. 13.8.1 wait mode the cop continues to operate duri ng wait mode. to prevent a cop reset during wait mode, periodicall y clear the cop counter in a cpu interrupt routine. 13.8.2 stop mode stop mode turns off the cgmxclk input to the cop and clears the sim counter. service the cop immediatel y before entering or after exiting stop mode to ensure a full cop timeout period a fter entering or exiting stop mode. 13.9 cop module during break mode the cop is disabled during a break interrupt when v dd +v hi is present on the rst pin. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC08KH12a ? rev. 1.0 data sheet motorola external interrupt (irq) 209 data sheet ? mc68HC08KH12a section 14. external interrupt (irq) 14.1 contents 14.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 14.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 14.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .210 14.4.1 irq1 pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 14.5 irq module during break interrupts . . . . . . . . . . . . . . . . . . . 213 14.6 irq status and control register (iscr) . . . . . . . . . . . . . . . . 213 14.2 introduction the irq module provides a non- maskable interrupt input. 14.3 features features of the irq modul e include the following: a dedicated external interrupt pin (irq1 ) irq1 interrupt control bits hysteresis buffer programmable edge-only or edge and level interrupt sensitivity automatic interrupt acknowledge irq1 pin includes inter nal pullup resistor f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external interrupt (irq) data sheet mc68HC08KH12a ? rev. 1.0 210 external interrupt (irq) motorola 14.4 functional description a logic zero applied to th e external interrupt pin can latch a cpu interrupt request. figure 14-1 shows the structure of the irq module. interrupt signals on the irq1 pin are latched into the irq1 latch. an interrupt latch remains set until on e of the following actions occurs: vector fetch ? a vector fetch au tomatically generates an interrupt acknowledge signal that clears the irq latch. software clear ? software can clea r the interrupt latch by writing to the acknowledge bit in the inte rrupt status and control register (iscr). writing a logic one to the ack1 bit cl ears the irq1 latch. reset ? a reset automatically clears the interrupt latch. the external interrupt pin is fal ling-edge-triggered and is software- configurable to be either falling-edge or low-leve l-triggered. the mode1 bit in the iscr controls the tr iggering sensitivity of the irq1 pin. when the interrupt pin is edge-trigger ed only, the cpu interrupt request remains set until a vector fetch, software clear, or reset occurs. when the interrupt pin is both fallin g-edge and low-leve l-triggered, the cpu interrupt request remains set unt il both of the following occur: vector fetch or software clear return of the interr upt pin to logic one the vector fetch or software clear ma y occur before or af ter the interrupt pin returns to logic one. as long as the pin is lo w, the interrupt request remains pending. a reset will clear th e latch and the mode1 control bit, thereby clearing the interrup t even if the pin stays low. when set, the imask1 bi t in the iscr mask al l external interrupt requests. a latched interrupt request is not pres ented to the interrupt priority logic unless t he imask1 bit is clear. note: the interrupt mask (i) in the conditi on code register (ccr) masks all interrupt requests, including external interrupt requests. (see 7.6 exception control .) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external interrupt (irq) functional description mc68HC08KH12a ? rev. 1.0 data sheet motorola external interrupt (irq) 211 figure 14-1. irq module block diagram 14.4.1 irq1 pin a logic zero on the irq1 pin can latch an interrup t request into the irq1 latch. a vector fetch, software cl ear, or reset clears the irq1 latch. if the mode1 bit is set, the irq1 pin is both falling-edge-sensitive and low-level-sensitive. with mode1 set, both of the follow ing actions must occur to clear irq1: ack1 imask1 dq ck clr irq1 high interrupt to mode select logic irq1 ff request irq1 v dd mode1 voltage detect synchro- nizer irqf1 to cpu for bil/bih instructions vector fetch decoder internal address bus reset v dd i nternal pullup device table 14-1. irq i/o po rt register summary addr. register name bit 7654321bit 0 $001e irq status/control register (iscr) read: 0000irqf10 imask1 mode1 write: ack1 reset:00000000 = unimplemented f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external interrupt (irq) data sheet mc68HC08KH12a ? rev. 1.0 212 external interrupt (irq) motorola vector fetch or software clear ? a vector fetc h generates an interrupt acknowledge signal to cl ear the latch. software may generate the interrupt acknowledge sig nal by writing a logic one to the ack1 bit in the in terrupt status and cont rol register (iscr). the ack1 bit is useful in app lications that poll the irq1 pin and require software to clear the irq1 latch. writing to the ack1 bit prior to leaving an interrupt se rvice routine can also prevent spurious interrupts due to noise . setting ack1 d oes not affect subsequent transitions on the irq1 pin. a falling edge that occurs after writing to the ack1 bit latc hes another interr upt request. if the irq1 mask bit, imask1, is clear, the cpu loads the program counter with t he vector address at lo cations $fffa and $fffb. return of the irq1 pin to logic one ? as long as the irq1 pin is at logic zero, irq1 remains active. the vector fetch or software cl ear and the return of the irq1 pin to logic one may occur in any or der. the interrupt reques t remains pending as long as the irq1 pin is at logic zero. a rese t will clear the latch and the mode1 control bit, thereby clearing the interrupt even if the pin stays low. if the mode1 bit is clear, the irq1 pin is falling-edge-s ensitive only. with mode1 clear, a vector fe tch or software clear immediately clears the irq1 latch. the irqf1 bit in the iscr register can be used to check for pending interrupts. the irqf1 bit is not affe cted by the imask1 bit, which makes it useful in applications where polling is preferred. use the bih or bil in struction to read the logic level on the irq1 pin. note: when using the level-sensit ive interrupt trigger, av oid false interrupts by masking interrupt requests in the interrupt routine. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external interrupt (irq) irq module during break interrupts mc68HC08KH12a ? rev. 1.0 data sheet motorola external interrupt (irq) 213 14.5 irq module du ring break interrupts the system integration module (sim) c ontrols whether the irq1 latch can be cleared during the br eak state. the bcfe bi t in the break flag control register (bfcr) enables software to clear the latches during the break state. (see section 7. system inte gration module (sim) .) to allow software to clear the irq1 latch during a break interrupt, write a logic one to the bcfe bit. if a latc h is cleared during the break state, it remains cleared when the m cu exits the break state. to protect the latches during the break state, write a l ogic zero to the bcfe bit. with bcfe at logic zero (i ts default state), writing to the ack1 bit in the irq status and control regi ster during the br eak state has no effect on the irq latch. 14.6 irq status and control register (iscr) the irq status and control register (iscr) controls and monitors operation of the irq m odule. the iscr has the following functions: shows the state of the irq1 flag clears the irq1 latch masks irq1 and interrupt request controls triggering se nsitivity of the irq1 interrupt pin address: $001e bit 7654321bit 0 read: 0000irqf10 imask1 mode1 write: ack1 reset:00000000 = unimplemented figure 14-2. irq status and control register (iscr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . external interrupt (irq) data sheet mc68HC08KH12a ? rev. 1.0 214 external interrupt (irq) motorola irqf1 ? irq1 flag this read-only status bi t is high when the irq1 interrupt is pending. 1 = irq1 interrupt pending 0 = irq1 interrupt not pending ack1 ? irq1 interrupt request acknowledge bit writing a logic one to this write-onl y bit clears the irq1 latch. ack1 always reads as logic ze ro. reset cl ears ack1. imask1 ? irq1 interrupt mask bit writing a logic one to th is read/write bit dis ables irq1 interrupt requests. reset clears imask1. 1 = irq1 interrupt requests disabled 0 = irq1 interrupt requests enabled mode1 ? irq1 edge/level select bit this read/write bit cont rols the triggering se nsitivity of the irq1 pin. reset clears mode1. 1 = irq1 interrupt requests on falling edges and low levels 0 = irq1 interrupt requests on falling edges only f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC08KH12a ? rev. 1.0 data sheet motorola keyboard interrupt module (kbi) 215 data sheet ? mc68HC08KH12a section 15. keyboard interrupt module (kbi) 15.1 contents 15.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 15.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 15.4 port-d keyboard interrupt block diagram . . . . . . . . . . . . . . . 218 15.4.1 port-d keyboard inte rrupt functional description . . . . . . . 219 15.4.2 port-d keyboard initiali zation. . . . . . . . . . . . . . . . . . . . . . . 220 15.4.3 port-d keyboard interr upt registers . . . . . . . . . . . . . . . . . 221 15.4.3.1 port-d keyboard status and control register: . . . . . . . 221 15.4.3.2 port-d keyboard interrupt en able register . . . . . . . . . . 222 15.5 port-e keyboard interrupt block diagram . . . . . . . . . . . . . . . 224 15.5.1 port-e keyboard inte rrupt functional description . . . . . . . 225 15.5.2 port-e keyboard initiali zation . . . . . . . . . . . . . . . . . . . . . . . 226 15.5.3 port-e keyboard interr upt registers . . . . . . . . . . . . . . . . . 227 15.5.3.1 port-e keyboard status and control register . . . . . . . . 227 15.5.3.2 port-e keyboard in terrupt enable register . . . . . . . . . . 228 15.6 port-f keyboard interrupt block di agram. . . . . . . . . . . . . . . . 230 15.6.1 port-f keyboard interrupt functi onal description . . . . . . . 231 15.6.2 port-f keyboard initia lization . . . . . . . . . . . . . . . . . . . . . . . 232 15.6.3 port-f keyboard interrupt register s . . . . . . . . . . . . . . . . . 233 15.6.3.1 port-f keyboard status and control register . . . . . . . . 233 15.6.3.2 port-f keyboard interrupt enab le register . . . . . . . . . . 234 15.6.3.3 port-f pull-up enabl e register . . . . . . . . . . . . . . . . . . . 235 15.7 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 15.8 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 15.9 keyboard module during break interrupts . . . . . . . . . . . . . . . 235 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . data sheet mc68HC08KH12a ? rev. 1.0 216 keyboard interrupt module (kbi) motorola keyboard interrupt module (kbi) 15.2 introduction the keyboard module provides twen ty independently maskable external interrupts which are accessibl e via ptd7-ptd0, pte3-pte0 and ptf7-ptf0. though the functionality of the three keyboard interrupts on the three ports is similar, the implementation is quite different. on port-d, enabling keyboard interrupt on a pin also enables its internal pull-up device. on port-e, the pull-up device is control by the pepex bit resided in the port-e keyboard interrupt e nable register (kbe ier). on port-f, the pull-up device is cont rol by the pfpex bit resided in the port-f control register (pfper). 15.3 features twenty keyboard interrupt pins with separate keyboard interrupt enable bits and three keyboard interrupt masks. hysteresis buffers internal pull-ups. programmable edge-only or edge- and level- interr upt sensitivity exit from low -power modes f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . keyboard interrupt module (kbi) features mc68HC08KH12a ? rev. 1.0 data sheet motorola keyboard interrupt module (kbi) 217 table 15-1. kbi i/o register summary addr. register name bit 7654321bit 0 $000c port d keyboard status and control register (kbdscr) read: 0000keydf0 imaskd moded write: ackd reset:00000000 $000d port d keyboard interrupt enable register (kbdier) read: kbdie7 kbdie6 kbdie5 kbdie4 kbdie3 kbdie2 kbdie1 kbdie0 write: reset:00000000 $000e port e keyboard status and control register (kbescr) read: 0000 keyef 0 imaske modee write: acke reset:00000000 $000f port e keyboard interrupt enable register (kbeier) read: pepe3 pepe2 pepe1 pepe0 kbeie3 kbeie2 kbeie1 kbeie0 write: reset:00000000 $0040 port f keyboard status and control register (kbfscr) read: 0000 keyff 0 imaskf modef write: ackf reset:00000000 $0041 port f keyboard interrupt enable register (kbfier) read: kbfie7 kbfie6 kbfie5 kbfie4 kbfie3 kbfie2 kbfie1 kbfie0 write: reset:00000000 $0042 port f pull-up enable register (pfper) read: pfpe7 pfpe6 pfpe5 pfpe4 pfpe3 pfpe2 pfpe1 pfpe0 write: reset:11111111 = unimplemented f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . data sheet mc68hc08k h12a ? rev. 1.0 218 keyboard interrupt module (kbi) motorola keyboard interrupt module (kbi) 15.4 port-d keyboard interrupt block diagram figure 15-1. port-d keyboar d interrupt bl ock diagram kbdie0 kbdie7 . . . port-d dq ck clr v dd moded imaskd keyboard interrupt ff vector fetch decoder ackd internal bus reset to pullup enable kbd7 kbd0 to pullup enable synchronizer keydf keyboard interrupt request f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . keyboard interrupt module (kbi) port-d keyboard interrupt block diagram mc68HC08KH12a ? rev. 1.0 data sheet motorola keyboard interrupt module (kbi) 219 15.4.1 port-d keyboard inte rrupt functional description writing to the kbdie7?kbdie0 bits in the keyboard interrupt enable register independently enables or disables each port d pin as a keyboard interrupt pin. enabling a keyboard interr upt pin in port-d also enables its internal pullup device. a logic 0 appli ed to an enabled keyboard interrupt pin latches a keyboard interrupt request. a keyboard interrupt is latched w hen one or more keyboard pins goes low after all were high. the moded bit in the keyboard status and control register controls the triggering mode of the keyboard interrupt. if the keyboard interrupt is e dge-sensitive only, a falling edge on a keyboard pin does not latch an in terrupt reques t if another keyboard pin is already low. to pr event losing an interrupt request on one pin because another pin is still low, software can disable the latter pin wh ile it is low. if the keyboard interrupt is falli ng edge- and low level-sensitive, an interrupt request is present as long as any keyboard pin is low. if the moded bit is set, the keyboar d interrupt pins are both falling edge- and low level-sensitive, and both of t he following actions must occur to clear a keyboard interrupt request: vector fetch or software clear ? a vector fetc h generates an interrupt acknowledge signal to clear the interrupt request. software may generate the inte rrupt acknowle dge signal by writing a logic 1 to the ackd bit in the keyboard status and control register kbdscr. the ackd bit is useful in applications that poll the keyboard interrupt pins and require software to clear the keyboard interrupt request. writing to the ackd bit prior to leaving an interrupt service routine can al so prevent spurious interrupts due to noise. setting a ckd does not affect subsequent transitions on the keyboard interrupt pins. a falling edge that occurs after writing to the ackd bi t latches another inte rrupt request. if the keyboard interrupt mask bit, imask d, is clear, the cpu loads the program counter with the vector address at locations $ffea and $ffeb. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . data sheet mc68HC08KH12a ? rev. 1.0 220 keyboard interrupt module (kbi) motorola keyboard interrupt module (kbi) return of all enabled keyboard interr upt pins to logic 1 ? as long as any enabled keyboard interrupt pin is at logic 0, the keyboard interrupt remains set. the vector fetch or software clear and the return of all enabled keyboard interrupt pins to logic 1 may occur in any order. if the moded bit is clear, the keyboard interrupt pin is falling-edge-sensitive only. with moded clear, a vector fetch or software clear immediately clear s the keyboard interrupt request. reset clears the keyboard interrupt request and the mod ed bit, clearing the interrupt request even if a keyboard interrupt pin stays at logic 0. the keyboard flag bit (keydf) in t he keyboard status and control register can be used to s ee if a pending interrupt exists. the keydf bit is not affected by the keyboard interrupt mask bit (imaskd) which makes it useful in applicati ons where polling is preferred. to determine the logi c level on a keyboard inte rrupt pin, use the data direction register to configure the pin as an input and read the data register. note: setting a keyboard interrupt enab le bit (kbdiex) forces the corresponding keyboard interrupt pin to be an input, overriding the data direction register. however, the data direction regist er bit must be a logic 0 for software to read the pin. 15.4.2 port-d key board initialization when a keyboard interrupt pin is enabl ed, it takes time for the internal pullup to reach a logic 1. therefore a false interr upt can occur as soon as the pin is enabled. to prevent a false interrupt on keyboard initialization: 1. mask keyboard interrupts by se tting the imaskd bit in the keyboard status and control register. 2. enable the kbi pins by setting the appropriate kbdiex bits in the keyboard interrupt enable register. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . keyboard interrupt module (kbi) port-d keyboard interrupt block diagram mc68HC08KH12a ? rev. 1.0 data sheet motorola keyboard interrupt module (kbi) 221 3. write to the ackd bit in the keyboard status and control register to clear any false interrupts. 4. clear the imaskd bit. an interrupt signal on an edg e-triggered pin can be acknowledged immediately after enabling the pin. an interrupt si gnal on an edge- and level-triggered interrupt pin must be acknowledged afte r a delay that depends on the external load. another way to avoid a fa lse interrupt for port-d: 1. configure the keyboard pins as outputs by setting the appropriate ddrd bits in data di rection register d. 2. write logic 1s to the appropriate port-d data register bits. 3. enable the kbdi pins by setting the appropriate kbdiex bits in the keyboard interrupt enable register. 15.4.3 port-d keyboar d interrupt registers 15.4.3.1 port-d keyboard st atus and control register: flags keyboard interrupt requests. acknowledges keyboard interrupt requests. masks keyboard interrupt requests. controls keyboard interrupt triggering sensitivity. bits [7:4] ? not used address: $000c bit 7654321bit 0 read: 0000keydf0 imaskd moded write: ackd reset:00000000 = unimplemented figure 15-2. port-d keyboard stat us and control regi ster (kbdscr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . data sheet mc68HC08KH12a ? rev. 1.0 222 keyboard interrupt module (kbi) motorola keyboard interrupt module (kbi) these read-only bits alwa ys read as logic 0s. keydf ? port-d keyboard flag bit this read-only bit is set when a keyboard interrupt is pending on port-d. reset clears the keydf bit. 1 = keyboard interrupt pending 0 = no keyboard interrupt pending ackd ? port-d key board acknowledge bit writing a logic 1 to th is write-only bit clears the keyboard interrupt request on port-d. ackd always reads as logic 0. reset clears ackd. imaskd ? port-d keyboard interrupt mask bit writing a logic 1 to th is read/write bit prev ents the output of the keyboard interrupt mask from generatin g interrupt req uests on port-d. reset clears the imaskd bit. 1 = keyboard interrupt requests masked 0 = keyboard interrupt requests not masked moded ? port-d keyboard tr iggering sensitivity bit this read/write bit controls the tri ggering sensitivity of the keyboard interrupt pins on port-d. reset clears moded. 1 = keyboard interrupt reques ts on falling edges and low levels 0 = keyboard interrupt requests on falling edges only 15.4.3.2 port-d keyboard interrupt enable register the port-d keyboard interrup t enable register enables or disables each port-d pin to operate as a keyboard interrupt pin. address: $000d bit 7654321bit 0 read: kbdie7 kbdie6 kbdie5 kbdie4 kbdie3 kbdie2 kbdie1 kbdie0 write: reset:00000000 figure 15-3. port-d keyboard interrupt enabl e register (kbdier) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . keyboard interrupt module (kbi) port-d keyboard interrupt block diagram mc68HC08KH12a ? rev. 1.0 data sheet motorola keyboard interrupt module (kbi) 223 kbdie7?kbdie0 ? port-d ke yboard interrupt enable bits each of these read/write bits enables the corres ponding keyboard interrupt pin on port-d to latch inte rrupt requests. reset clears the keyboard interrupt enable register. 1 = kbdx pin enabled as ke yboard interrupt pin 0 = kbdx pin not enabled as keyboard interrupt pin f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . data sheet mc68hc08k h12a ? rev. 1.0 224 keyboard interrupt module (kbi) motorola keyboard interrupt module (kbi) 15.5 port-e keyboard interrupt block diagram figure 15-4. port-e keyboar d interrupt block diagram kbeie0 kbeie3 . . . dq ck clr v dd modee imaske keyboard interrupt ff vector fetch decoder acke internal bus reset kbe3 kbe0 synchronizer keyef port-e keyboard interrupt request pepe0 pepe3 to pullup enable to pullup enable f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . keyboard interrupt module (kbi) port-e keyboard interrupt block diagram mc68HC08KH12a ? rev. 1.0 data sheet motorola keyboard interrupt module (kbi) 225 15.5.1 port-e keyboard inte rrupt functional description writing to the kbeie3?kbeie0 bits in the keyboard interrupt enable register independently enables or disables each port e pin as a keyboard interrupt pin. enabling a keyboard interr upt pin in port-e does not enable its internal pullup device . writing to the pepe3?pepe0 bits in the keyboard interrupt enable register independently enables or disables each port e pin pull-up dev ice. a logic 0 a pplied to an enabled keyboard interrupt pin latches a keyboard interrupt request. a keyboard interrupt is latched w hen one or more keyboard pins goes low after all were high. the modee bit in the keyboard status and control register controls the triggering mode of the keyboard interrupt. if the keyboard interrupt is e dge-sensitive only, a falling edge on a keyboard pin does not latch an in terrupt reques t if another keyboard pin is already low. to pr event losing an interrupt request on one pin because another pin is still low, software can disable the latter pin wh ile it is low. if the keyboard interrupt is falli ng edge- and low level-sensitive, an interrupt request is present as long as any keyboard pin is low. if the modee bit is set, the keyboard interrupt pins ar e both falling edge- and low level-sensitive, and both of t he following actions must occur to clear a keyboard interrupt request: vector fetch or software clear ? a vector fetc h generates an interrupt acknowledge signal to clear the interrupt request. software may generate the inte rrupt acknowle dge signal by writing a logic 1 to t he acke bit in the keyboa rd status and control register kbescr. the acke bit is useful in applications that poll the keyboard interrupt pins and require software to clear the keyboard interrupt request. writing to the acke bit prior to leaving an interrupt service routine can al so prevent spurious interrupts due to noise. setting acke does not affect subsequent transitions on the keyboard interrupt pins. a falling edge that occurs after writing to the acke bi t latches another inte rrupt request. if the keyboard interrupt mask bit, imask e, is clear, the cpu loads the program counter with the vector address at locations $ffec and $ffed. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . data sheet mc68HC08KH12a ? rev. 1.0 226 keyboard interrupt module (kbi) motorola keyboard interrupt module (kbi) return of all enabled keyboard interr upt pins to logic 1 ? as long as any enabled keyboard interrupt pin is at logic 0, the keyboard interrupt remains set. the vector fetch or software clear and the return of all enabled keyboard interrupt pins to logic 1 may occur in any order. if the modee bit is clear, t he keyboard interrupt pin is falling-edge-sensitive only. with modee clear, a vector fetch or software clear immediately clear s the keyboard interrupt request. reset clears the keyboard interrupt request and the modee bit, clearing the interrupt request even if a keyboard interrupt pin stays at logic 0. the keyboard flag bit (keyef) in t he keyboard status and control register can be used to see if a pending interrupt exists. the keyef bit is not affected by the keyboard interrupt mask bit (imaske) which makes it useful in applicati ons where polling is preferred. to determine the logi c level on a keyboard inte rrupt pin, disable the pull-up device, use the da ta direction register to configure the pin as an input and then read t he data register. note: setting a keyboard interrupt enab le bit (kbeiex) forces the corresponding keyboard interrupt pin to be an input, overriding the data direction register. 15.5.2 port-e key board initialization when a keyboard interrupt pin is enabl ed, it takes time for the internal pullup to reach a logic 1. therefore a false interr upt can occur as soon as the pin is enabled. to prevent a false interrupt on keyboard initialization: 1. mask keyboard interrupts by se tting the imaske bit in the keyboard status and control register. 2. write to ddrex bits to make port pin an input pin. 3. enable the kbi pins by setting the appropriate kbe iex bits in the keyboard interrupt enable register. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . keyboard interrupt module (kbi) port-e keyboard interrupt block diagram mc68HC08KH12a ? rev. 1.0 data sheet motorola keyboard interrupt module (kbi) 227 4. write to the acke bit in the keyboard status and control register to clear any false interrupts. 5. clear the imaske bit. an interrupt signal on an edg e-triggered pin can be acknowledged immediately after enabling the pin. an interrupt si gnal on an edge- and level-triggered interrupt pin must be acknowledged afte r a delay that depends on the external load. 15.5.3 port-e keyboar d interrupt registers 15.5.3.1 port-e keyboard status and control register flags keyboard interrupt requests. acknowledges keyboard interrupt requests. masks keyboard interrupt requests. controls keyboard interrupt triggering sensitivity. bits [7:4] ? not used these read-only bits alwa ys read as logic 0s. keyef ? port-e keyboard flag bit this read-only bit is set when a keyboard interrupt is pending on port-e. reset clears the keyef bit. 1 = keyboard interrupt pending 0 = no keyboard interrupt pending address: $000e bit 7654321bit 0 read: 0000 keyef 0 imaske modee write: acke reset:00000000 = unimplemented figure 15-5. port-e keyboard status and contro l register (kbescr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . data sheet mc68HC08KH12a ? rev. 1.0 228 keyboard interrupt module (kbi) motorola keyboard interrupt module (kbi) acke ? port-e key board acknowledge bit writing a logic 1 to th is write-only bit clears the keyboard interrupt request on port-e. acke al ways reads as logic 0. reset clears acke. imaske ? port-e keyboard interrupt mask bit writing a logic 1 to th is read/write bit prev ents the output of the keyboard interrupt mask from generati ng interrupt requests on port-e. reset clears the imaske bit. 1 = keyboard interrupt requests masked 0 = keyboard interrupt requests not masked modee ? port-e keyboard tr iggering sensitivity bit this read/write bit controls the tri ggering sensitivity of the keyboard interrupt pins on port-e. reset clears modee. 1 = keyboard interrupt reques ts on falling edges and low levels 0 = keyboard interrupt requests on falling edges only 15.5.3.2 port-e keyboard interrupt enable register the port-e keyboard interrupt enable register enables or disables each port-e pin to operate as a keyboa rd interrupt pin and to enable and disable the pullup devic e on each port-e pin. pepe3?pepe0 ? port-e pull-up enable bits each of these read/write bits enable or disable the pul l-up device on the corresponding port-e pin. reset clears these bits. 1 = pepex pull-up device enabled. 0 = pepex pull-up device disabled. address: $000f bit 7654321bit 0 read: pepe3 pepe2 pepe1 pepe0 kbeie3 kbeie2 kbeie1 kbeie0 write: reset:00000000 figure 15-6. port-e keyboard interrupt enabl e register (kbeier) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . keyboard interrupt module (kbi) port-e keyboard interrupt block diagram mc68HC08KH12a ? rev. 1.0 data sheet motorola keyboard interrupt module (kbi) 229 kbeie3?kbeie0 ? port-e ke yboard interrupt enable bits each of these read/write bits enables the corres ponding keyboard interrupt pin on port-d to latch inte rrupt requests. reset clears the keyboard interrupt enable register. 1 = kbex pin enabled as ke yboard interrupt pin 0 = kbedx pin not enabled as keyboard interrupt pin f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . data sheet mc68hc08k h12a ? rev. 1.0 230 keyboard interrupt module (kbi) motorola keyboard interrupt module (kbi) 15.6 port-f keyboard interrupt block diagram figure 15-7. port-f keyboard interrupt block diagram kbfie0 kbfie7 . . . dq ck clr v dd modef imaskf keyboard interrupt ff vector fetch decoder ackf internal bus reset kbf3 kbf0 synchronizer keyff port-f keyboard interrupt request pfpe0 pfpe7 to pullup enable to pullup enable f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . keyboard interrupt module (kbi) port-f keyboard in terrupt block diagram mc68HC08KH12a ? rev. 1.0 data sheet motorola keyboard interrupt module (kbi) 231 15.6.1 port-f keyboard inte rrupt functional description writing to the kbfie7?k bfie0 bits in the ke yboard interrupt enable register independently enables or disables each port f pin as a keyboard interrupt pin. enabling a keyboard in terrupt pin in por t-f does not enable its internal pullup device. writing to the pfpe7?pfpe0 bits in the pull-up enable register independently enables or disables each port f pin pull-up device. a logi c 0 applied to an enabled keyboard interrupt pin latches a keyboard interrupt request. a keyboard interrupt is latched w hen one or more keyboard pins goes low after all were high. the modef bit in the keyboard status and control register controls the triggering mode of the keyboard interrupt. if the keyboard interrupt is e dge-sensitive only, a falling edge on a keyboard pin does not latch an in terrupt reques t if another keyboard pin is already low. to pr event losing an interrupt request on one pin because another pin is still low, software can disable the latter pin wh ile it is low. if the keyboard interrupt is falli ng edge- and low level-sensitive, an interrupt request is present as long as any keyboard pin is low. if the modef bit is set, the keyboard interrupt pi ns are both falling edge- and low level-sensitive, and both of t he following actions must occur to clear a keyboard interrupt request: vector fetch or software clear ? a vector fetc h generates an interrupt acknowledge signal to clear the interrupt request. software may generate the inte rrupt acknowle dge signal by writing a logic 1 to t he ackf bit in the keyboard status and control register kbfscr. the ackf bit is useful in applications that poll the keyboard interrupt pins and require software to clear the keyboard interrupt request. writing to the ackf bit prior to leaving an interrupt service routine can al so prevent spurious interrupts due to noise. setting ackf does not affect subsequent transitions on the keyboard interrupt pins. a falling edge that occurs after writing to the ackf bi t latches another interr upt request. if the keyboard interrupt mask bit, imaskf, is clear, the cpu loads the program counter with the vector address at locations $ffe8 and $ffe9. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . data sheet mc68HC08KH12a ? rev. 1.0 232 keyboard interrupt module (kbi) motorola keyboard interrupt module (kbi) return of all enabled keyboard interr upt pins to logic 1 ? as long as any enabled keyboard interrupt pin is at logic 0, the keyboard interrupt remains set. the vector fetch or software clear and the return of all enabled keyboard interrupt pins to logic 1 may occur in any order. if the modef bit is clear, the keyboard interrupt pin is falling-edge-sensitive only. with modef clear, a vector fetch or software clear immediately clear s the keyboard interrupt request. reset clears the keyboard interrupt request and the modef bit, clearing the interrupt request even if a keyboard interrupt pin stays at logic 0. the keyboard flag bit (key ff) in the keyboard status and control register can be used to see if a pend ing interrupt exists. the keyff bit is not affected by the keyboard interrupt mask bit (imaskf) which makes it useful in applicati ons where polling is preferred. to determine the logi c level on a keyboard inte rrupt pin, disable the pull-up device, use the da ta direction register to configure the pin as an input and then read t he data register. note: setting a keyboard interrupt enab le bit (kbfiex) forces the corresponding keyboard interrupt pin to be an input, overriding the data direction register. 15.6.2 port-f keybo ard initialization when a keyboard interrupt pin is enabl ed, it takes time for the internal pullup to reach a logic 1. therefore a false interr upt can occur as soon as the pin is enabled. to prevent a false interrupt on keyboard initialization: 1. mask keyboard interrupts by se tting the imaskf bit in the keyboard status and control register. 2. write to ddrfx bits to ma ke the port pin an input pin. 3. enable the kbi pins by setting the appropriate kbfiex bits in the keyboard interrupt enable register. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . keyboard interrupt module (kbi) port-f keyboard in terrupt block diagram mc68HC08KH12a ? rev. 1.0 data sheet motorola keyboard interrupt module (kbi) 233 4. write to the ackf bit in the keyboard status and control register to clear any false interrupts. 5. clear the imaskf bit. an interrupt signal on an edg e-triggered pin can be acknowledged immediately after enabling the pin. an interrupt si gnal on an edge- and level-triggered interrupt pin must be acknowledged afte r a delay that depends on the external load. 15.6.3 port-f keyboar d interrupt registers 15.6.3.1 port-f keyboard status and control register flags keyboard interrupt requests. acknowledges keyboard interrupt requests. masks keyboard interrupt requests. controls keyboard interrupt triggering sensitivity. bits [7:4] ? not used these read-only bits alwa ys read as logic 0s. keyff ? port-f keyboard flag bit this read-only bit is set when a keyboard interrupt is pending on port-f. reset clear s the keyff bit. 1 = keyboard interrupt pending 0 = no keyboard interrupt pending address: $0040 bit 7654321bit 0 read: 0000 keyff 0 imaskf modef write: ackf reset:00000000 = unimplemented figure 15-8. port-f keyboard st atus and control r egister (kbfscr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . data sheet mc68HC08KH12a ? rev. 1.0 234 keyboard interrupt module (kbi) motorola keyboard interrupt module (kbi) ackf ? port-f keyboard acknowledge bit writing a logic 1 to th is write-only bit clears the keyboard interrupt request on port-f. a ckf always reads as logi c 0. reset clears ackf. imaskf ? port-f keyboard interrupt mask bit writing a logic 1 to th is read/write bit prev ents the output of the keyboard interrupt mask from generati ng interrupt requests on port-f. reset clears the imaskf bit. 1 = keyboard interrupt requests masked 0 = keyboard interrupt requests not masked modef ? port-f keyboard tr iggering sensitivity bit this read/write bit controls the tri ggering sensitivity of the keyboard interrupt pins on port- f. reset clears modef. 1 = keyboard interrupt reques ts on falling edges and low levels 0 = keyboard interrupt requests on falling edges only 15.6.3.2 port-f keyboard interrupt enable register the port-f keyboard interr upt enable register enabl es or disables each port-f pin to operate as a keyboard interrupt pin. kbfie7?kbfie0 ? port-f key board interrupt enable bits each of these read/write bits enables the corres ponding keyboard interrupt pin on port-f to latch in terrupt requests. reset clears the keyboard interrupt enable register. 1 = kbfx pin enabled as keyboard interrupt pin 0 = kbfx pin not enabled as keyboard interrupt pin address: $0041 bit 7654321bit 0 read: kbfie7 kbfie6 kbfie5 kbfie4 kbfie3 kbfie2 kbfie1 kbfie0 write: reset:00000000 figure 15-9. port-f keyboard inte rrupt enable regi ster (kbfier) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . keyboard interrupt module (kbi) wait mode mc68HC08KH12a ? rev. 1.0 data sheet motorola keyboard interrupt module (kbi) 235 15.6.3.3 port-f pu ll-up enable register the pull-up enable regist er enables or disables the pull-up device for port f. pfpe7?pfpe0 ? port f pull-up enable bits these read/write bits enable/disable the pull-up device. reset sets ddrf7?ddrf0 to ?1?s, enabling all port f pull-up devices. 1 = corresponding port f pin pull-up device enabled 0 = corresponding port f pi n pull-up device disabled 15.7 wait mode the keyboard modules remain active in wait mode. cl earing the imaskx bit in the keyboard status and contro l register enables keyboard interrupt requests to bring the mcu out of wait mode. 15.8 stop mode the keyboard modules remain active in stop mode. clearing the imaskx bit in the keyboard status and control regist er enables keyboard interrupt requests to bring the mcu out of stop mode. 15.9 keyboard module during break interrupts the system integration module (sim) controls whether the keyboard interrupt latch cam be cl eared during the break st ate. the bcfe bit in address: $0042 bit 7654321bit 0 read: pfpe7 pfpe6 pfpe5 pfpe4 pfpe3 pfpe2 pfpe1 pfpe0 write: reset:11111111 figure 15-10. port f pull- up enable register (pfper) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . data sheet mc68HC08KH12a ? rev. 1.0 236 keyboard interrupt module (kbi) motorola keyboard interrupt module (kbi) the break flag control regi ster (bfcr) enables software to clear status bits during the break state. to allow software to clear the key board interrupt la tch during a break interrupt, write a logic 1 to the bcfe bit. if a latch is cleared during the break state, it remains cleared w hen the mcu exits the break state. to protect the latch during the break st ate, write a logi c 0 to the bcfe bit. with bcfe at logi c 0 (its default state), writing to the keyboard acknowledge bit (ackx) in the key board status and control register during the break state has no effect. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC08KH12a ? rev. 1.0 data sheet motorola break module (brk) 237 data sheet ? mc68HC08KH12a section 16. break module (brk) 16.1 contents 16.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 16.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 16.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238 16.4.1 flag protection during break interr upts . . . . . . . . . . . . . . . 240 16.4.2 cpu during break interrupts . . . . . . . . . . . . . . . . . . . . . . .240 16.4.3 tim during break interr upts . . . . . . . . . . . . . . . . . . . . . . . . 240 16.4.4 cop during break interrupts . . . . . . . . . . . . . . . . . . . . . . . 240 16.5 break module registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 16.5.1 break status and control regist er (brkscr) . . . . . . . . . 241 16.5.2 break address registers (brk h and brkl). . . . . . . . . . . 241 16.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 16.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .242 16.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .242 16.2 introduction this section describes the break module. the break module can generate a break interrupt that stops normal program flow at a defined address to enter a background program. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . break module (brk) data sheet mc68HC08KH12a ? rev. 1.0 238 break module (brk) motorola 16.3 features features of the break m odule include the following: accessible i/o registers during the break interrupt cpu-generated break interrupts software-generated break interrupts cop disabling during break interrupts 16.4 functional description when the internal address bus matches the value written in the break address registers, the br eak module issues a breakpoint signal (bkpt ) to the sim. the sim then causes the cpu to load t he instruction register with a software interrupt instruction (swi) after completi on of the current cpu instruction. the program coun ter vectors to $fffc and $fffd ($fefc and $fefd in monitor mode). the following events can cause a break interrupt to occur: a cpu-generated address (the addr ess in the program counter) matches the contents of th e break address registers. software writes a logic one to t he brka bit in the break status and control register. when a cpu generated addre ss matches the contents of the break address registers, th e break interrupt begins af ter the cpu completes its current instruction. a return from in terrupt instruction (rti) in the break routine ends the break interrupt and returns the mcu to normal operation. figure 16-1 shows the structure of the break module. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . break module (brk) functional description mc68HC08KH12a ? rev. 1.0 data sheet motorola break module (brk) 239 figure 16-1. break module block diagram iab[15:8] iab[7:0] 8-bit comparator 8-bit comparator control break address register low break address register high iab[15:0] bkpt (to sim) table 16-1. break i/o register summary addr. register name bit 7654321bit 0 $fe0c break address register high (brkh) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset:00000000 $fe0d break address register low (brkl) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset:00000000 $fe0e break status/control register (brkscr) read: brke brka 000000 write: reset:00000000 = unimplemented f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . break module (brk) data sheet mc68HC08KH12a ? rev. 1.0 240 break module (brk) motorola 16.4.1 flag protectio n during break interrupts the system integration module (sim) controls whether or not module status bits can be clea red during the break stat e. the bcfe bit in the break flag control register (bfcr) enabl es software to clear status bits during the break state. (see 7.8.3 break flag cont rol register (bfcr) and see the break interrupts subsection for each module.) 16.4.2 cpu during break interrupts the cpu starts a br eak interrupt by: loading the instruction regist er with the swi instruction loading the program counter wi th $fffc:$fffd ($fefc:$fefd in monitor mode) the break interrupt begins after completion of t he cpu instruction in progress. if the break address register match occurs on the last cycle of a cpu instruction, the break interrupt begins immediately. 16.4.3 tim during break interrupts a break interrupt stops the timer counter. 16.4.4 cop during break interrupts the cop is disabled during a break interrupt when v dd +v hi is present on the rst pin. 16.5 break module registers three registers control and monito r operation of t he break module: break status and cont rol register (brkscr) break address regi ster high (brkh) break address regi ster low (brkl) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . break module (brk) break module registers mc68HC08KH12a ? rev. 1.0 data sheet motorola break module (brk) 241 16.5.1 break status and control register (brkscr) the break status and control register contains break module enable and status bits. brke ? break enable bit this read/write bit enabl es breaks on break address register matches. clear brke by writing a logic zero to bit 7. reset clears the brke bit. 1 = breaks enabled on 16-bit address match 0 = breaks disabled brka ? break active bit this read/write status and control bit is se t when a break address match occurs. writing a logic one to brka generates a break interrupt. clear brka by writing a logic zero to it before exiting the break routine. reset clears the brka bit. 1 = break address match 0 = no break address match 16.5.2 break address re gisters (brkh and brkl) the break address registers contai n the high and low bytes of the desired breakpoint address. reset cl ears the break ad dress registers. address: $fe0e bit 7654321bit 0 read: brke brka 000000 write: reset:00000000 = unimplemented figure 16-2. break status an d control register (brkscr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . break module (brk) data sheet mc68HC08KH12a ? rev. 1.0 242 break module (brk) motorola 16.6 low-power modes the wait and stop in structions put the mcu in low-power- consumption standby modes. 16.6.1 wait mode if enabled, the break module is active in wait mode. in the break routine, the user can subtract one from the re turn address on the stack if sbsw is set (see 7.7 low-power modes ). clear the sbsw bi t by writing logic zero to it. 16.6.2 stop mode a break interrupt causes exit from stop mode and sets the sbsw bit in the break status register. see 7.8 sim registers . address: $fe0c bit 7654321bit 0 read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset:00000000 address: $fe0d bit 7654321bit 0 read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset:00000000 figure 16-3. break addr ess registers (brkh and brkl) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC08KH12a ? rev. 1.0 data sheet motorola electrical specifications 243 data sheet ? mc68HC08KH12a section 17. electrical specifications 17.1 contents 17.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 17.3 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 244 17.4 functional operating range. . . . . . . . . . . . . . . . . . . . . . . . . . 245 17.5 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 17.6 dc electrical characterist ics . . . . . . . . . . . . . . . . . . . . . . . . . 246 17.7 control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 17.8 oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 17.9 timer interface module characterist ics . . . . . . . . . . . . . . . . . 247 17.10 clock generation module characteristics . . . . . . . . . . . . . . . 248 17.10.1 cgm component specifications . . . . . . . . . . . . . . . . . . . . 248 17.10.2 cgm electrical specif ications . . . . . . . . . . . . . . . . . . . . . . 248 17.10.3 acquisition/lock time specifications . . . . . . . . . . . . . . . . . 249 17.2 introduction this section contains electrical and timing specifications. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications data sheet mc68HC08KH12a ? rev. 1.0 244 electrical specifications motorola 17.3 absolute maximum ratings maximum ratings are t he extreme limits to which the mcu can be exposed without perman ently damaging it. note: this device is not guar anteed to operate properly at the maximum ratings. refer to 17.6 dc electrical characteristics for guaranteed operating conditions. note: this device contains circ uitry to protect the i nputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid applic ation of any voltage higher than maximum-rated voltages to this hi gh-impedance circui t. for proper operation, it is recommended that v in and v out be constrained to the range v ss (v in or v out ) v dd . reliability of operation is enhanced if unused inputs are co nnected to an appropriate logic voltage level (for example, either v ss or v dd .) characteristic (1) 1. voltages referenced to v ss . symbol value unit supply voltage v dd ?0.3 to +6.0 v input voltage (except usb port pins) v in v ss ?0.3 to v dd +0.3 v programming voltage v pp v ss ?0.3 to 14.0 v usb port pins v usb ?1 to 4.6 v maximum current per pin excluding v dd and v ss i 25 ma storage temperature t stg ?55 to +150 c maximum current out of v ss i mvss 100 ma maximum current into v dd i mvdd 100 ma f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications functional operating range mc68HC08KH12a ? rev. 1.0 data sheet motorola electrical specifications 245 17.4 functional operating range 17.5 thermal characteristics characteristic symbol value unit operating temperature range t a 0 to 85 c operating voltage range v dd 4.0 to 5.5 v characteristic symbol value unit thermal resistance qfp (64 pins) ja 70 c/w i/o pin power dissipation p i/o user determined w power dissipation (1) p d p d = (i dd x v dd ) + p i/o = k/(t j + 273 c) w constant (2) k p d x (t a + 273 c ) + p d 2 ja w/ c average junction temperature t j t a + (p d ja ) c maximum junction temperature t jm 100 c notes 1. power dissipation is a function of temperature. 2. k is a constant unique to the de vice. k can be determined for a known t a and measured p d. with this value of k, p d and t j can be determined for any value of t a . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications data sheet mc68HC08KH12a ? rev. 1.0 246 electrical specifications motorola 17.6 dc electrical characteristics characteristic symbol min typ (2) max unit usb regulator output voltage v regout 3.0 3.3 3.6 output high voltage, (i load = ?2.0ma) all i/o pins v oh v dd ? 0.8 ? ? v output low voltage, (i load = 1.6ma) all i/o pins v ol ??0.4v input high voltage all ports, irq1 , rst , osc1 v ih 0.7 v dd ?v dd v input low voltage all ports, irq1 , rst , osc1 v il v ss ?0.3 v dd v output high current (v oh = 2.1v) port c in ldd mode i oh 34.56ma output low current (v ol = 2.3v) port c in ldd mode i ol 10 15 20 ma v dd supply current run, usb active, pll on, f op = 6.0mhz (3) run, usb suspended, pll off, f op = 1.5mhz (3) wait (4) stop (5) 0 c to 85 c i dd ? ? ? ? ? ? ? ? 34 18 6 350 ma ma ma a i/o ports hi-z leakage current i il ?? 10 a input current i in ?? 1 a capacitance ports (as input or output) c out c in ? ? ? ? 12 8 pf por rearm voltage (6) v por 0?100mv por rise time ramp rate (7) r por 0.035 ? ? v/ms monitor mode entry voltage v dd +v hi 1.5 v dd 9v pullup resistor pa0-pa7, pb0-pb7, pc0-pc4, pd0-pd7, pe0- pe3, pf0-pf7, rst , irq1 r pu 20 35 50 k ? schmitt trigger input high level pd0-pd7, pe0-pe3, pf0-pf7 v shi 2.8 3.4 v schmitt trigger input low level pd0-pd7, pe0-pe3, pf0-pf7 v shl 1.7 2.3 v notes: 1. v dd = 4.0 to 5.5 vdc, v ss = 0 vdc, t a = t l to t h , unless otherwise noted. 2. typical values reflect average meas urements at midpoint of voltage range, 25 c only. 3. run (operating) i dd measured using external square wave clock source. all inputs 0.2 v from rail. no dc loads. less than 100 pf on all outputs. c l = 20 pf on osc2. all ports configured as out puts. osc2 capacitance linearly affects run i dd . measured with all modules enabled. 4. wait i dd measured using external s quare wave clock source (f cgmxclk = 6 mhz); all inputs 0.2 v from rail; no dc loads; less than 100 pf on all outputs. c l = 20 pf on osc2; usb in suspend mode, 15 k ? 5% termination resistors on d+ and d? pins; all ports config- ured as inputs; osc2 capacit ance linearly affects wait i dd . 5. stop i dd measured with usb in suspend mode, osc1 grounded, 1.425 k ? 1% pull-up resistor on d+ pin and 15 k ? 1% pull- down resistors on d+ and d? pins, no port pins sourcing current. 6. maximum is highest vo ltage that por is guaranteed. 7. if minimum v dd is not reached before the inter nal por reset is released, rst must be driven low exte rnally until minimum v dd is reached. 8. r pu is measured at v dd = 5.0v. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications control timing mc68HC08KH12a ? rev. 1.0 data sheet motorola electrical specifications 247 17.7 control timing 17.8 oscillator characteristics 17.9 timer interface module characteristics characteristic symbol min max unit internal operating frequency (2) f op ?6mhz rst input pulse width low (3) t irl 50 ? ns notes: 1. v dd = 4.0 to 5.5 vdc, v ss = 0 vdc; timing shown with respect to 20% v dd and 70% v dd , unless otherwise noted. 2. some modules may require a minimum frequency greater th an dc for proper operation; see appropriate table for this information. 3. minimum pulse width reset is guaranteed to be recognized. it is possible for a smaller pulse width to cause a reset. characteristic symbol min typ max unit crystal frequency (1) f cgmxclk ? 6 ? mhz external clock reference frequency (1), (2) f cgmxclk dc ? 24 mhz crystal load capacitance (3) c l ?? ? crystal fixed capacitance (3) c 1 ?2 c l ? crystal tuning capacitance (3) c 2 ?2 c l ? feedback bias resistor r b ?10 ? m ? series resistor (3), (4) r s ?? ? notes: 1. the usb module is designed to function at f cgmxclk = 6mhz and cgmvclk = 48mhz. the values given here are oscillator specifications. 2. no more than 10% duty cycle deviation from 50% 3. consult crystal vendor data sheet 4. not required for high frequency crystals characteristic symbol min max unit input capture pulse width t tih, t til 125 ? ns input clock pulse width t tch, t tcl (1/f op ) + 5 ? ns f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications data sheet mc68HC08KH12a ? rev. 1.0 248 electrical specifications motorola 17.10 clock generation module characteristics 17.10.1 cgm component specifications 17.10.2 cgm electri cal specifications characteristic symbol min typ max unit crystal reference frequency (1) 1. fundamental mode crystals only f xclk 6mhz crystal load capacitance (2) 2. consult crystal manufacturer?s data. c l ???pf crystal fixed capacitance (2) c 1 20 pf crystal tuning capacitance (2) c 2 20 pf feedback bias resistor r b 10 m ? series resistor r s 0k ? notes: description symbol min typ max unit operating voltage v dd 4.0 ? 5.5 v operating temperature t 0 25 70 o c crystal reference frequency f rclk 6mhz vco center-of-range frequency f vrs 48 mhz vco multiply factor n 1 ? 4095 vco prescale multiplier 2 p 118 reference divider factor r 1 1 15 vco operating frequency f vclk 40 ? 56 mhz f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications clock generation modu le characteristics mc68HC08KH12a ? rev. 1.0 data sheet motorola electrical specifications 249 17.10.3 acquisition/ lock time specifications description symbol min typ max notes filter capacitor multiply factor c fact ? 0.0145 ? f/s v acquisition mode time factor k acq ?0.117?v tracking mode time factor k trk ?0.021?v manual mode time to stable t acq ??if c f chosen correctly manual stable to lock time t al ??if c f chosen correctly manual acquisition time t lock ?t acq + t al ? tracking mode entry frequency to l e r a n c e ? trk 0? 3.6% acquisition mode entry frequency to l e r a n c e ? acq 6.3% ? 7.2% lock entry frequency tolerance ? lock 0? 0.9% lock exit frequency tolerance ? unl 0.9% ? 1.8% reference cycles per acquisition mode measurement n acq 32 ? reference cycles per tracking mode measurement n trk 128 ? automatic mode time to stable t acq n acq /f rdv ?if c f chosen correctly automatic stable to lock time t al n trk /f rdv ?if c f chosen correctly automatic lock time t lock ?t acq + t al ? 8v dda f rdv k acq ----------------------------- - 4v dda f rdv k trx ----------------------------- 8v dda f rdv k acq ----------------------------- - 4v dda f rdv k trx ----------------------------- f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications data sheet mc68HC08KH12a ? rev. 1.0 250 electrical specifications motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC08KH12a ? rev. 1.0 data sheet motorola mechanical specifications 251 data sheet ? mc68HC08KH12a section 18. mechanical specifications 18.1 contents 18.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 18.3 64-pin quad flat pack (qfp) . . . . . . . . . . . . . . . . . . . . . . . . . 252 18.4 52-pin low-profile quad flat pack (lqfp) . . . . . . . . . . . . . . 253 18.2 introduction this section gives t he dimensions for: 64-pin plastic quad fl at pack (case no. 840c) 52-pin low-profile quad flat pack (case no. 848d) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mechanical specifications data sheet mc68HC08KH12a ? rev. 1.0 252 mechanical specifications motorola 18.3 64-pin quad flat pack (qfp) figure 18-1. 64-pin quad -flat-pack (case no. 840c) g h e c detail a l a 48 s l ?d? ?a? ?b? 0.05 (0.002) a?b s a?b m 0.20 (0.008) d s h s a?b m 0.20 (0.008) d s c b v 0.05 (0.002) d s a?b m 0.20 (0.008) d s h s a?b m 0.20 (0.008) d s c seating plane datum plane ?c? ?h? 49 33 32 64 17 1 16 detail c 0.10 (0.004) s a?b m 0.20 (0.008) d s c section b?b f n d base j metal detail a p bb ?a?, ?b?, ?d? notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. datum plane ?h? is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums a?b and ?d? to be determined at datum plane ?h?. 5. dimensions s and v to be determined at seating plane ?c?. 6. dimensions a and b do not include mold protrusion. allowable protrusion is 0.25 (0.010) per side. dimensions a and b do include mold mismatch and are determined at datum plane ?h?. 7. dimension d does not include dambar protrusion. dambar protrusion shall not cause the d dimension to exceed 0.53 (0.021). dambar cannot be located on the lower radius or the foot. 8. dimension k is to be measured from the theoretical intersection of lead foot and leg centerlines. dim min max min max inches millimeters a 13.90 14.10 0.547 0.555 b 13.90 14.10 0.547 0.555 c 2.07 2.46 0.081 0.097 d 0.30 0.45 0.012 0.018 e 2.00 0.079 f 0.30 0.012 g 0.80 bsc 0.031 bsc ? h 0.067 0.250 0.003 0.010 j 0.130 0.230 0.005 0.090 k l 12.00 ref 0.472 ref m n 0.130 0.170 0.005 0.007 p 0.40 bsc 0.016 bsc q r 0.13 0.30 0.005 0.012 s 16.20 16.60 0.638 0.654 t 0.20 ref 0.008 ref u v 16.20 16.60 0.638 0.654 x 1.10 1.30 0.043 0.051 2.40 0.094 ? detail c seating plane m u t r q k x m 5 5 10 10 2 2 8 8 0 0 ?? 0.660 0.020 0.026 0.500 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mechanical specifications 52-pin low-profile quad flat pack (lqfp) mc68HC08KH12a ? rev. 1.0 data sheet motorola mechanical specifications 253 18.4 52-pin low-profil e quad flat pack (lqfp) figure 18-2. 52-pin low-profile quad flat pack (case no. 848d) f notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. datum plane ?h? is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums ?l?, ?m? and ?n? to be determined at datum plane ?h?. 5. dimensions s and v to be determined at seating plane ?t?. 6. dimensions a and b do not include mold protrusion. allowable protrusion is 0.25 (0.010) per side. dimensions a and b do include mold mismatch and are determined at datum plane ?h?. 7. dimension d does not include dambar protrusion. dambar protrusion shall not cause the lead width to exceed 0.46 (0.018). minimum space between protrusion and adjacent lead or protrusion 0.07 (0.003). view aa ab ab view y section ab?ab rotated 90 clockwise dim a min max min max inches 10.00 bsc 0.394 bsc millimeters a1 5.00 bsc 0.197 bsc b 10.00 bsc 0.394 bsc b1 5.00 bsc 0.197 bsc c ??? 1.70 ??? 0.067 c1 0.05 0.20 0.002 0.008 c2 1.30 1.50 0.051 0.059 d 0.20 0.40 0.008 0.016 e 0.45 0.030 f 0.22 0.35 0.009 0.014 g 0.65 bsc 0.75 0.018 0.026 bsc j 0.07 0.20 0.003 0.008 k 0.50 ref 0.020 ref r1 0.08 0.20 0.003 0.008 s 12.00 bsc 0.472 bsc s1 6.00 bsc 0.236 bsc u 0.09 0.16 0.004 0.006 v 12.00 bsc 0.472 bsc v1 6.00 bsc 0.236 bsc w 0.20 ref 0.008 ref z 1.00 ref 0.039 ref c l ?x? x=l, m, n 1 13 14 26 27 39 40 52 4x 13 tips 4x n 0.20 (0.008) h l?m n 0.20 (0.008) t l?m seating plane c 0.10 (0.004) t 4x 3 4x 2 s 0.05 (0.002) 0.25 (0.010) gage plane c2 c1 w k e z s l?m m 0.13 (0.005) n s t plating base metal d j u b v b1 a s v1 a1 s1 ?l? ?n? ?m? ?h? ?t? 1 g 1 3 2 0 0 0 0 7 12 12 12 12 7 ??? ??? ref ref 3x view y view aa 2x r r1 ref ref f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mechanical specifications data sheet mc68HC08KH12a ? rev. 1.0 254 mechanical specifications motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . how to reach us: usa/europe/locations not listed: motorola literature distribution p.o. box 5405 denver, colorado 80217 1-800-521-6274 or 480-768-2130 japan: motorola japan ltd. sps, technical information center 3-20-1, minami-azabu, minato-ku tokyo 106-8573, japan 81-3-3440-3569 asia/pacific: motorola semiconductors h.k. ltd. silicon harbour centre 2 dai king street tai po industrial estate tai po, n.t., hong kong 852-26668334 home page: http://motorola.com/semiconductors mc68HC08KH12a/d rev. 1 3/2004 information in this document is provided solely to enable system and software implementers to use motorola products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability , including without limitation consequential or incidental damages. ?typical? parameters that may be provided in motorola data sheets and/or specifications can and do vary in differen t applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and the stylized m logo are registered in the us patent and trademark office. all other product or service names are the property of their respective owners. motorola, inc. is an equal opportunity/affirmative action employer. ? motorola inc. 2004 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . |
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